Senior Staff Front-End Design Engineer RTL Design RISC-V
Bitdeer is a technology company providing Bitcoin mining solutions.
Maintainer signals as of 9/25/2026
Funding history
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About Bitdeer
Bitdeer provides full-spectrum Bitcoin mining and high-performance computing solutions, including SEALMINER mining equipment, Minerbase cooling containers, cloud mining, co-mining, mining management applications, mining rights marketplaces, and large-scale data center operations. The company also offers AI cloud infrastructure with GPU computing, model training and deployment capabilities, and turnkey AI data center solutions for enterprise customers and developers. Bitdeer is headquartered in Singapore and operates globally.
Skills
Candidate Availability
Required and preferred rules are kept separate and reflect the wording in the original posting.
About the Role
Integrate commercial RISC-V core soft IP with external accelerators, tailor CPU features to meet performance, power, and area requirements, modify Verilog and SystemVerilog RTL, collaborate across ASIC design disciplines, support synthesis and timing closure, optimize power and floorplanning, and contribute to verification and debugging across pre-silicon and post-silicon stages.
Requirements
- Master’s or Bachelor’s degree in Electrical Engineering, Computer Engineering, or Computer Science with a focus on computer architecture.
- Familiarity with the RISC-V ISA, custom extensions, extension instruction interfaces, privilege modes, and CSRs.
- Hands-on experience with CPU core integration, technical specification drafting, and IP feature tailoring.
- Extensive Verilog RTL development experience using industry-standard tools.
- Experience collaborating with performance modeling or engineering teams, middle-end engineers, and back-end engineers.
- Knowledge of synthesis flows, linting, CDC/RDC analysis, and static timing analysis.
- Knowledge of SoC-level power-saving techniques, clocking architectures, reset and power-up sequences, low-power microarchitecture, DFT, DFX, and MBIST.
- Ability to write Python, Perl, Shell, or TCL scripts.
Responsibilities
- Integrate commercial RISC-V core soft IP with external accelerators using custom extension instruction interfaces.
- Tailor CPU soft IP features and microarchitecture to meet performance, power, and area requirements.
- Modify and enhance Verilog and SystemVerilog RTL for processor front-end and control-path functionality.
- Collaborate with performance, middle-end, and back-end engineering teams on IP integration and system-level optimization.
- Drive front-end ASIC implementation activities including synthesis, static timing analysis closure, power reduction, and floorplanning.
- Contribute to design verification and debug logic issues during pre-silicon and post-silicon stages.
Benefits
- A culture that values authenticity and diversity of thoughts and backgrounds.
- An inclusive and respectful environment with open workspaces and startup spirit.
- Fast-growing company with opportunities to network with industry pioneers and enthusiasts.
- Ability to contribute directly to the future of the digital asset industry.
- Involvement in new projects and development of processes and systems.
- Personal accountability, autonomy, fast growth, and learning opportunities.
- Attractive welfare benefits and developmental opportunities such as training and mentoring.
