ASIC Physical Design Engineer - DFT, Senior

Positron AI builds hardware and software for energy-efficient generative-AI and Transformer-model inference.

Series CRecently funded
Reno, Nevada, United States
About Positron AI

Reno-based AI-infrastructure company whose currently shipping Atlas inference server is complemented by planned Asimov custom accelerator silicon and Titan inference systems.

View jobs by Positron AI

Skills

Candidate Availability

Required and preferred rules are kept separate and reflect the wording in the original posting.

About the Role

You will own DFT implementation end-to-end, from micro-architecture through tapeout and first silicon. You will implement scan, compression, ATPG, memory BIST, boundary scan and IJTAG, integrate DFT IP, verify DFT pre-silicon, partner with physical design, and use AI tools to boost engineering productivity.

Requirements

  • BS, MS, or PhD in Electrical or Computer Engineering
  • 8+ years of ASIC development experience
  • Extensive hands-on DFT implementation on complex SoCs with multiple production tapeouts
  • Deep understanding of scan architectures, ATPG, memory BIST, boundary scan, IJTAG, EDT
  • Hands-on experience with Siemens Tessent DFT solutions
  • Strong RTL design skills in Verilog/SystemVerilog
  • Practical experience with synthesis and gate-level verification
  • Strong scripting in Python, Tcl, Perl, or similar
  • Excellent debugging skills
  • Ability to drive cross-functional technical execution

Responsibilities

  • Micro-architect and implement DFT instrumentation logic including scan insertion, compression, ATPG, memory BIST, boundary scan, IJTAG, and debug features
  • Integrate DFT IP into internal RTL and evaluate third-party DFT IP
  • Work directly in RTL, synthesis, and DFT tool flows
  • Develop DFT verification plans and validate through simulation and gate-level verification
  • Drive stuck-at, transition, cell-aware, and power-aware ATPG strategies
  • Work with backend teams on physical realization of DFT architecture
  • Guide scan chain partitioning, compression planning, and test clock architecture
  • Address power-aware test, timing closure, and test mode integration
  • Partner across RTL design, verification, physical design, test, firmware, and silicon validation
  • Leverage AI tools to improve engineering productivity

Benefits

  • Equity
  • Fully company-paid medical, dental, and vision insurance for you and dependents
  • Company-paid life and disability coverage
  • Supplemental hospital, critical illness, and accident coverage available
  • Unlimited paid time off
  • 13 paid company holidays
  • Remote-first culture with company-provided computer and home office setup
  • 401(k) with company matching from day one
ASIC Physical Design Engineer - DFT, Senior at Positron AI | JobStash