RTL Design Engineer, Networking / NoC
AI research and deployment company building and deploying frontier AI products, including ChatGPT, Codex, and its API platform.
Projects
About OpenAI
OpenAI’s mission is to ensure artificial general intelligence benefits all of humanity. It consists of the nonprofit OpenAI Foundation and OpenAI Group, a public benefit corporation governed by the Foundation.
Skills
Candidate Availability
Required and preferred rules are kept separate and reflect the wording in the original posting.
About the Role
You'll help design and develop next-generation AI accelerator silicon, working across architecture, microarchitecture, and RTL implementation. You'll translate complex system and performance requirements into efficient, scalable hardware designs, collaborating closely with silicon architects, hardware and software engineers, verification, and physical design teams. You'll have opportunities to influence architectural decisions and own RTL design from concept through integration.
Requirements
- Strong hands-on experience with ASIC RTL design and microarchitecture using SystemVerilog or Verilog
- Experience designing complex digital hardware blocks from specification through RTL and verification
- Understanding of hardware architecture tradeoffs including performance, power, area, latency, and throughput
- Experience collaborating across architecture, software, verification, and physical design teams
- Experience with synthesis, timing closure, and physical implementation
- Experience with NoC, networking, interconnect fabrics, or high-bandwidth data movement
- Candidates may need to meet legal status requirements under U.S. export control laws
Responsibilities
- Design and implement high-performance RTL for AI accelerator silicon from microarchitecture through integration
- Collaborate with architecture and software teams to translate system requirements into microarchitectures
- Drive hardware/software co-design to optimize performance, power, area, and scalability
- Develop and optimize RTL for datapaths, control logic, and interconnects
- Evaluate tradeoffs across bandwidth, latency, throughput, and resource utilization
- Partner with design and formal verification teams to ensure functional correctness and debug issues
- Work with physical design teams to optimize RTL for synthesis, timing closure, power, and area
- Contribute to architecture reviews and design specifications
- Support block-level and SoC-level integration, debugging, and performance optimization
Benefits
- Medical, dental, and vision insurance with HSA employer contributions
- Health FSA, Dependent Care FSA, and commuter pre-tax accounts
- 401(k) with employer match
- Paid parental leave up to 24 weeks for birth parents and 20 weeks for non-birthing parents
- Paid medical and caregiver leave up to 8 weeks
- Flexible PTO for exempt employees
- 13+ paid company holidays and company office closures
- Paid sick or safe time
- Mental health and wellness support
- Employer-paid basic life and disability coverage
- Annual learning and development stipend
- Daily meals in offices and meal delivery credits
- Relocation support for eligible employees
- Equity
- Performance-related bonus
- Charitable donation matching and wellness stipends
