Sr/Staff Digital Design Engineer

Skills

About the Role

You will develop SystemVerilog RTL modules with DFT in mind, debug complex logic and mixed-signal simulations, and integrate silicon photonic communication and compute technology into digital accelerator design. You will collaborate with architecture, verification, physical design, photonic, analog and software teams, write specifications and documentation, and manage RTL implementation to meet schedules.

Requirements

• Bachelor's degree in Electrical or Computer Engineering or related field
• At least 5 years of experience in ASIC or high-speed chip design with multiple successful tape outs
• Proficiency in SystemVerilog or Verilog
• Experience debugging complex logic and mixed-signal simulations with EDA tools such as Synopsys VCS, Cadence Xcelium, Questa
• Track record of delivering high-performance, low-power digital designs in advanced process nodes
• Ability to comply with U.S. export control laws

Responsibilities

• Develop RTL (SystemVerilog) modules with DFT considerations for IC development
• Debug complex logic and mixed-signal simulations
• Integrate silicon photonic communication and compute technology into digital accelerator design
• Work with Architecture, Design Verification, Physical Design, Photonic, Analog and Software teams
• Create design specifications and documentation for partner teams
• Generate documentation for modules including functionality and timing
• Manage RTL implementation to deliver correct, performant designs on schedule by mitigating risks

Benefits

• Comprehensive Health Care Plan (Medical, Dental & Vision)
• Retirement Savings Matching Program
• Life Insurance (Basic, Voluntary & AD&D)
• Generous Time Off (Vacation, Sick & Public Holidays)
• Paid Family Leave
• Short Term & Long Term Disability
• Training & Development
• Commuter Benefits
• Flexible, hybrid workplace model
• Equity grants (applicable to full-time employees)
• New hire equity grant and annual performance-based equity