RTL Designer
Velaura AI develops ultra-low-power silicon and software technologies for AI compute infrastructure.
Funding history
About Velaura AI, Inc.
Velaura AI is an AI compute infrastructure company developing ultra-low-power silicon and software technologies. Its Titan Core™ platform uses proprietary digital chip IP, low-voltage libraries, EDA flows, and design methodologies to improve performance per watt in AI accelerators while maintaining performance, yield, and reliability. The company also applies this technology to Physical AI systems, including industrial robots, autonomous machines, drones, humanoids, and edge devices. Velaura engages hyperscalers, XPU companies, and developers of next-generation AI infrastructure and Physical AI solutions.
Skills
Candidate Availability
Required and preferred rules are kept separate and reflect the wording in the original posting.
About the Role
You will design, implement, and optimize RTL for core SoC components. You will collaborate on microarchitecture and hardware-software co-design, define hardware interfaces and execution flows, analyze performance bottlenecks, improve implementations, and partner with verification and physical design throughout development.
Requirements
- Experience designing RTL for complex digital systems
- Strong understanding of computer architecture, microarchitecture, and digital design fundamentals
- Experience with Verilog, SystemVerilog, and modern RTL design methodologies
- Familiarity with performance, power, and area tradeoffs
- Understanding of memory systems, interconnects, caches, DMA engines, or accelerator architectures
- Experience with hardware-software co-design and system-level performance optimization
- Strong debugging and problem-solving skills
- Ability to work effectively in a collaborative, multidisciplinary engineering environment
Responsibilities
- Design, implement, and optimize RTL for key SoC components
- Collaborate with architects to develop microarchitectures
- Participate in hardware-software co-design discussions
- Define hardware interfaces, execution flows, memory hierarchies, and performance-critical interactions
- Contribute to compute engines, memory subsystems, interconnect fabrics, control processors, DMA engines, and power-management logic
- Optimize designs for performance, power, area, scalability, and reliability
- Partner with verification and physical design teams throughout development
- Analyze performance bottlenecks and propose architectural and implementation improvements
- Use AI-assisted development workflows to improve productivity, quality, and design exploration
- Participate in design reviews
Benefits
- Equity compensation
- Medical coverage
- Dental coverage
- Vision coverage
- Paid time off
- Flexible work arrangements