Design Verification Engineer Internal IP
Etched is an AI-hardware company building rack-scale frontier inference clusters.
Funding history
About Etched
Etched co-designs chips, racks, software, and manufacturing systems for efficient inference of frontier AI models, targeting throughput, latency, cost, and power efficiency across prefill and decode workloads.
Skills
Candidate Availability
Required and preferred rules are kept separate and reflect the wording in the original posting.
About the Role
You will verify custom chip IP such as systolic arrays, DMA engines, network-on-chip components, and memory subsystems. You will build UVM and SystemVerilog testbenches, execute verification plans, debug RTL and protocol issues, and improve reusable verification infrastructure. You will also work with architecture, RTL, software, firmware, and emulation counterparts to support end-to-end bring-up and debug coverage.
Requirements
- UVM
- SystemVerilog
- Digital design debugging
- Computer architecture
- Digital design
- Datapath verification or memory system verification or interconnect verification
Responsibilities
- Develop and maintain UVM and SystemVerilog testbenches for high-performance IP
- Define and execute verification plans for correctness, corner cases, concurrency, and performance
- Debug datapath and protocol issues in RTL and testbench environments
- Validate functionality and design intent with architects and designers
- Partner with software, firmware, and emulation teams on bring-up and debug coverage
- Contribute to reusable verification infrastructure, coverage models, and methodology improvements
Benefits
- Medical, dental, and vision coverage
- $500 per month credit for waiving medical benefits
- Wellness benefits
- Daily lunch and dinner in the office
- Unlimited compute budget subject to ROI justification