Physical Design Engineer - Synth, Senior

Skills

About the Role

You will own synthesis, timing convergence and implementation readiness for key partitions across an AI accelerator roadmap. You will turn high-quality RTL into implementation-ready netlists, develop and maintain timing constraints, and drive physical-aware optimization with RTL designers and backend partners. You will also help strengthen and scale synthesis methodology and apply AI tools to improve timing analysis and automation.

Requirements

• 8+ years of ASIC implementation experience, including at least two successful tapeouts
• Strong hands-on proficiency in synthesis and flow development
• Proven experience closing timing on complex, multi-million-gate designs
• Deep knowledge of Cadence Genus and/or Synopsys Design Compiler
• Strong SDC expertise including MMMC environments
• Solid grasp of RTL design principles and implementation-friendly coding
• Hands-on experience with advanced process nodes (7nm and below preferred)
• Strong Tcl and Python scripting ability
• Excellent debugging and root-cause analysis skills
• Authorized to work in the U.S.; no new visa sponsorship (H-1B transfers considered)

Responsibilities

• Own synthesis for assigned partitions and subsystems, delivering clean, high-QoR netlists on schedule
• Improve synthesis flows including constraint development, timing budgeting, QoR optimization, incremental synthesis and hierarchical implementation
• Help define and apply signoff criteria for synthesis deliverables
• Run synthesis using Cadence Genus and Synopsys Design Compiler or equivalent
• Develop and maintain SDC constraints, clock definitions, false paths, multicycle paths, generated clocks and MMMC environments
• Track and improve synthesis QoR for your blocks
• Drive logical timing closure across frequency, area, power, congestion and wireability
• Perform root-cause analysis of timing bottlenecks and contribute to chip-level timing budgets
• Resolve timing risks with architecture and RTL teams before physical implementation
• Partner with backend engineers on physical-aware synthesis, retiming, register balancing, pipeline optimization and logic restructuring
• Give RTL teams actionable feedback for implementation-friendly designs
• Collaborate with architecture, RTL, verification, physical design, DFT, IP providers and design services
• Review QoR, timing and area reports with external implementation partners
• Apply AI tools to timing analysis, QoR regression, constraint generation, debug, report analysis and automation

Benefits

• Fully company-paid medical, dental and vision insurance for you and dependents
• Company-paid life and disability coverage
• Supplemental hospital, critical illness and accident coverage available
• Unlimited paid time off
• 13 paid company holidays
• Remote-first culture with company-provided computer and home office setup
• Equity
• 401(k) with company matching from day one