ASIC Logic Design Engineer, Senior

Skills

About the Role

You will lead the definition, implementation and delivery of critical IP blocks and subsystems for inference ASICs/SoCs. You will own microarchitecture through RTL signoff, integrate high-performance interconnects and memory interfaces, drive lint, CDC/RDC, DFT and synthesis, develop methodology and automation, partner with verification and architecture, and mentor junior engineers.

Requirements

• BS/MS in EE/CE or related with 8+ years of ASIC/SoC RTL design experience
• Proven track record leading designs from spec to signoff
• Deep SystemVerilog RTL expertise including clocking, resets, CDC/RDC
• Extensive experience with front-end flows (lint, CDC, synthesis/STA, DFT)
• Hands-on expertise with at least three of: HBM/DDR, PCIe/CXL, AMBA AXI/ACE/CHI, cache/memory hierarchies, high-throughput datapaths
• Strong cross-functional communication skills

Responsibilities

• Define and document microarchitecture for complex IP blocks and subsystems
• Deliver production-quality parameterized SystemVerilog RTL
• Lead lint, CDC/RDC, DFT integration, and synthesis bring-up
• Own PPA metrics and drive microarchitectural optimizations
• Architect and integrate interconnects (AXI/CHI/ACE), DMA engines, coherency logic, and memory interfaces (HBM/DDR)
• Engage with IP vendors and internal stakeholders
• Develop coding guidelines, reusable IP packaging, and signoff checklists
• Contribute automation flows (Python/Tcl/Make/CI)
• Partner with Verification on test plans and reference models
• Support bring-up, post-silicon debug, and customer engagements
• Mentor junior engineers and lead design reviews

Benefits

• Equity
• Comprehensive benefits
• Flexible work environment