DFT Engineer Architect Manager Senior Manager

Skills

About the Role

Lead Design-for-Test architecture, methodology, implementation, verification, and sign-off for complex ASIC and SoC designs. Drive test planning, pattern generation, coverage closure, memory and logic BIST strategies, silicon bring-up, yield analysis, production test support, DFT flow improvements, automation, implementation issue resolution, and engineer mentoring.

Requirements

• 15+ years of experience in DFT architecture, implementation, and sign-off for ASIC or SoC designs
• Experience leading DFT strategy for large-scale ASIC or SoC programs through silicon production
• Expertise in scan design, scan compression, ATPG, MBIST, LBIST, JTAG, boundary scan, IJTAG, test access architecture, and fault simulation
• Experience with ATPG pattern generation, coverage closure, pattern validation, diagnosis, and silicon correlation
• Experience leading DFT teams and cross-functional execution
• Experience with post-silicon debug, yield improvement, failure diagnosis, production test support, and field failure analysis
• Understanding of DFT impacts on RTL, physical design, timing closure, low-power implementation, and sign-off
• Experience with DFT and EDA tools
• Knowledge of advanced fault models and timing-aware ATPG

Responsibilities

• Define and drive DFT architecture, strategy, and methodology for complex ASIC and SoC designs
• Lead scan insertion, compression, ATPG, MBIST, LBIST, boundary scan, JTAG, IJTAG, test access mechanisms, and fault simulation
• Own end-to-end DFT execution from architecture through production ramp
• Develop test plans optimizing fault coverage, test cost, test quality, and manufacturability
• Drive ATPG pattern generation, coverage analysis, fault grading, diagnosis, and pattern validation
• Define memory test strategies, repair analysis, redundancy handling, and memory test integration
• Lead DFT verification, test-mode validation, and pattern verification
• Resolve DFT timing, congestion, test-mode constraint, scan reordering, and implementation closure issues
• Support post-silicon debug, yield analysis, failure diagnosis, production test correlation, and field failure analysis
• Establish DFT quality metrics, sign-off criteria, coverage targets, and execution checkpoints
• Improve DFT tools, flows, automation, and methodologies
• Lead and mentor DFT engineers

Benefits

• Performance-based incentives
• Equity participation
• Medical coverage
• Dental coverage
• Vision coverage
• Paid time off
• Flexible work arrangements

Hiring Process

Velaura may use AI tools to review applications, analyze resumes, assess responses, and identify inconsistencies or verification signals. These tools assist the recruitment team but do not replace human judgment; final hiring decisions are made by humans.