DFT Intern
EtchedVisit Etched website
Etched is an AI-hardware company building rack-scale frontier inference clusters.
San Jose, United States
Funding history
About Etched
Etched co-designs chips, racks, software, and manufacturing systems for efficient inference of frontier AI models, targeting throughput, latency, cost, and power efficiency across prefill and decode workloads.
Skills
Candidate Availability
Required and preferred rules are kept separate and reflect the wording in the original posting.
About the Role
You will review and refine DFT-flow automation for chip-level regression on Caelius. You will work with frontend and backend design groups, contribute to DFT verification simulations, and develop flows for ATPG fault models. You will support work involving MBIST, scan, boundary scan, SSN, and related DFT tooling and infrastructure.
Requirements
- Hardware description language
- Verilog or SystemVerilog
- ASIC design
- SoC design
- Digital logic design
- ASIC design flow
- Synthesis
- STA
- DFT
- Python
- Tcl
- Transformer
- Artificial intelligence
Responsibilities
- Review and refine DFT-flow automation for chip-level regression on Caelius
- Work with frontend and backend design teams
- Contribute to DFT verification simulations for MBIST, scan, BSCAN, and SSN
- Develop flows for ATPG fault models
Benefits
- 12-week paid internship
- Housing support for relocating interns
- Daily lunch and dinner in the office
- Direct mentorship