Design For Test Engineer

Skills

About the Role

You will develop DFT architectures for ASIC and SoC designs and integrate scan, boundary scan, BIST, and MBIST methodologies. You will plan and execute DFT verification, analyze silicon and test data, support bring-up and failure analysis, optimize ATE programs and test patterns, and document DFT architecture and procedures. You will also lead reviews, share DFT practices, and mentor others.

Requirements

• DFT engineering
• ASIC
• SoC
• Digital design
• Verification methodology
• SystemVerilog
• EDA tool
• Synopsys DFT Compiler
• Cadence Encounter Test
• Mentor Tessent
• Python
• Perl
• Tcl
• Testability analysis
• Debugging

Responsibilities

• Develop DFT architectures for ASIC and SoC designs
• Integrate scan insertion, boundary scan, BIST, and MBIST methodologies
• Ensure DFT requirements are addressed throughout the design cycle
• Analyze test results and silicon debug data to improve coverage, yield, and reliability
• Create and execute DFT verification plans
• Apply simulation-based and formal verification techniques to DFT logic
• Conduct DFT audits and design reviews
• Support silicon bring-up, debug, and failure analysis
• Develop and optimize ATE programs for volume production
• Generate production-quality test patterns and support failure analysis
• Implement test-process improvements with manufacturing and quality teams
• Maintain DFT architecture, test-plan, procedure, and debug documentation
• Deliver training, onboarding, and mentorship on DFT practices

Benefits

• Medical, dental, and vision coverage
• $500 per month credit for waiving medical benefits
• Housing subsidy of $2.5k per month for employees living within walking distance
• Relocation support for moves to San Jose
• Wellness benefits
• Daily lunch and dinner in the office
• Unlimited compute budget subject to ROI justification