Senior Design for Test Engineer
Positron AIVisit Positron AI website
Positron AI builds hardware and software for energy-efficient generative-AI and Transformer-model inference.
Reno, Nevada, United States
Funding history
Investors
About Positron AI
Reno-based AI-infrastructure company whose currently shipping Atlas inference server is complemented by planned Asimov custom accelerator silicon and Titan inference systems.
Skills
AsicAtpgBoundary ScanDebuggingDftEdtEmulationFailure AnalysisFpga PrototypingFuse ProgrammingHardware Root Of TrustHbmIjtagKey ManagementLow-Power DesignLpddrManufacturing TestMbistNetlistPalladiumPciePerlPythonRtlScanSecure BootSerdesSiliconSocSynthesisSystemverilogTclTessentVeloceVerificationVerilogYield EnhancementZebu
Candidate Availability
Required and preferred rules are kept separate and reflect the wording in the original posting.
About the Role
You will own end-to-end DFT implementation for AI accelerators, from micro-architecture definition through tapeout and first-silicon bring-up. You will implement and integrate DFT logic in RTL and third-party IP, validate it before silicon, guide physical implementation, and coordinate technical execution across engineering functions.
Requirements
- BS, MS, or PhD in Electrical Engineering or Computer Engineering.
- 8+ years of ASIC development experience.
- Extensive hands-on DFT implementation experience on complex SoCs with multiple successful production tapeouts.
- Deep knowledge of scan architectures, ATPG, memory BIST, boundary scan, IJTAG, EDT, fault models, and structural coverage analysis.
- Hands-on experience with Siemens Tessent DFT solutions, including SSN, EDT, MBIST, RTLpro, Scanpro, and Tessent Diagnosis.
- RTL design skills using Verilog or SystemVerilog.
- Experience with synthesis and gate-level verification.
- Scripting ability in Python, Tcl, Perl, or similar languages.
- Debugging skills across RTL, netlists, and silicon failure analysis.
- Ability to drive technical execution across cross-functional engineering teams.
- Current authorization to work in the United States.
Responsibilities
- Micro-architect and implement DFT instrumentation logic, including scan insertion, compression, ATPG, memory BIST, boundary scan, IJTAG, and debug features.
- Integrate DFT IP into internal RTL and evaluate third-party DFT IP.
- Develop DFT verification plans and validate functionality through simulation and gate-level verification.
- Drive ATPG strategies and ensure DFx coverage targets are achieved before tapeout.
- Guide scan-chain partitioning, compression planning, test-clock architecture, power-aware testing, timing closure, and test-mode integration.
- Partner with RTL, verification, physical design, package and test engineering, firmware, system software, and silicon validation through bring-up.
- Use AI tools for DFT report review, ATPG and coverage analysis, regression triage, documentation, and workflow automation.
Benefits
- Fully company-paid medical, dental, and vision insurance for employees and dependents.
- Company-paid life and disability coverage, with voluntary additional coverage options.
- Supplemental hospital, critical illness, and accident coverage.
- Unlimited paid time off.
- 13 paid company holidays.
- Remote-first work culture.
- Company-provided computer and home-office setup.
- Equity.
- 401(k) with company matching from day one.
- H-1B visa transfer support for eligible candidates.
