Senior Staff Physical Design Timing Engineer

Skills

About the Role

You will develop timing constraints and drive STA, timing closure, and tapeout signoff across synthesis through place and route. You will incorporate signoff corners, margins, and derates into timing flows; collaborate on timing modes and constraints; assess power, performance, and area tradeoffs; automate timing ECOs; and document best practices.

Requirements

• Bachelor’s degree in Electrical Engineering or Computer Engineering
• 12 years of Physical Design experience
• At least 5 years of hands-on ASIC STA, timing constraints development, and timing closure experience with Cadence or Synopsys tools
• Experience managing on-chip variation derates, multi-mode multi-corner constraints, and clock tree strategies
• Knowledge of TCL, Python, PERL, or Shell
• Problem-solving skills
• Clear communication skills

Responsibilities

• Drive STA signoff for silicon photonics chips
• Incorporate signoff corners, margins, and derates into timing analysis flows
• Develop timing modes and constraints for synthesis, place and route, and chip signoff flows
• Analyze power, performance, and area tradeoffs for chip implementation flows
• Run full-chip STA and project timing summaries across scenarios
• Automate timing ECO generation with Tempus or PrimeTime
• Document best practices and lessons learned

Benefits

• Comprehensive medical, dental, and vision health plan
• Retirement savings matching program
• Basic, voluntary, and AD&D life insurance
• Vacation, sick time, and public holidays
• Paid family leave
• Short-term and long-term disability coverage
• Commuter benefits
• Flexible hybrid workplace model
• Equity grants for eligible full-time employees