Senior Staff Front End Engineer RISC Processor Integration

Skills

About the Role

You will configure and integrate RISC-V or Arm processor IP into SoC platforms, customize processor features, develop RTL wrappers and system glue logic, integrate interconnects and interrupt controllers, support verification and system bring-up, resolve performance and power issues, and coordinate third-party IP integration.

Requirements

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field
• Five or more years of experience in SoC design, processor integration, or semiconductor development
• Experience integrating RISC processors, particularly RISC-V, into complex SoC platforms
• Understanding of pipeline architecture, cache hierarchy, MMU, MPU, PMP, interrupt and exception handling, and debug architecture
• Experience with AMBA AXI4, AHB, and APB protocols
• Strong Verilog and SystemVerilog RTL design skills
• Experience with synthesis, lint, CDC analysis, and RTL quality checks
• Familiarity with SoC boot flow and firmware interaction
• Experience with VCS, Xcelium, Questa, Verdi, or equivalent tools
• Understanding of clock and reset architecture and low-power design
• Experience with third-party IP vendors and architecture specifications

Responsibilities

• Configure and integrate RISC processor IP into SoC platforms
• Customize processor cache, memory management, protection, debug, interrupt, and privilege features
• Integrate processor subsystems with AXI, AHB, and APB interconnects and interrupt controllers
• Develop RTL integration logic, wrappers, and system glue logic
• Collaborate with verification teams on test plans and simulation debugging
• Work with firmware and software teams on bootloader, BSP, and operating system bring-up
• Resolve system-level performance, power, and integration issues
• Review third-party IP documentation and coordinate IP integration

Benefits

• Attractive welfare benefits