Senior or Staff Mid-End Engineer for Static Timing Analysis and Synthesis

Skills

About the Role

You will synthesize and optimize ASIC logic, perform static timing analysis and timing closure, implement low-power techniques, debug design issues, support test integration, collaborate on physical design constraints and bottlenecks, and verify synthesized netlists with formal equivalence tools.

Requirements

• Bachelor's or master's degree in Electrical Engineering, Computer Engineering, or a related field
• 3–7 years of IC design experience focused on synthesis, timing closure, and power optimization
• Proficiency in Verilog and SystemVerilog
• Proficiency in RTL-to-GDSII flows
• Experience with Synopsys Design Compiler, Cadence Genus, PrimeTime, and Innovus
• Strong understanding of timing analysis, multi-clock domain handling, and clock tree synthesis
• Familiarity with AXI, NoC, mesh, and torus interconnect architectures
• Experience with UPF, power gating, and dynamic voltage scaling
• Proficiency in TCL, Python, Perl, and shell scripting

Responsibilities

• Perform logic synthesis and optimization for ASIC designs
• Conduct static timing analysis, constraint tuning, and clock tree synthesis
• Optimize critical paths in multi-clock domains and high-frequency data pipelines
• Implement clock gating, power gating, and dynamic voltage scaling
• Optimize memory hierarchies to reduce energy consumption
• Collaborate on scan-chain insertion, MBIST, and JTAG integration
• Debug synthesis, timing, and power issues before physical implementation
• Collaborate on floorplanning, place and route, congestion analysis, and timing bottlenecks
• Provide design constraints for high-speed interconnects, NoCs, and large-scale data movement
• Verify synthesized netlist correctness using formal verification and equivalence-checking tools