Physical Design Engineer - Block Level, Subsystem Implementation
EtchedVisit Etched website
Etched is an AI-hardware company building rack-scale frontier inference clusters.
Maintainer signals as of 9/24/2026
San Jose, United States
Funding history
About Etched
Etched co-designs chips, racks, software, and manufacturing systems for efficient inference of frontier AI models, targeting throughput, latency, cost, and power efficiency across prefill and decode workloads.
Skills
AtpgCadenceClock Tree SynthesisDrcEcoElectromigrationFloorplanningFormal VerificationFusion CompilerGdsiiGenusInnovusIr DropLvsPerlPhysical DesignPhysical VerificationPlacementPower VerificationPpaPrimetimePythonRc ExtractionRoutingRtlScan InsertionStaSynopsysSynthesisTclTempusTiming ClosureUpfVoltus
Candidate Availability
Required and preferred rules are kept separate and reflect the wording in the original posting.
About the Role
You will own end-to-end block-level and subsystem physical design, from synthesis through GDSII sign-off. You will drive timing and sign-off closure, improve power, performance, and area, support hierarchical integration, and oversee outsourced physical-design work.
Requirements
- 5–10+ years of physical-design experience
- Experience with RTL synthesis through GDSII sign-off tools, flows, and methodology
- Experience with back-end design and timing closure on 5 nm or below process nodes
- Experience with Cadence Innovus and Genus or Synopsys Fusion Compiler flows
- Experience with sign-off tools such as PrimeTime, Tempus, or Voltus
- Experience with UPF-based low-power design, power verification, synthesis, scan insertion, ATPG, formal verification, floorplanning, placement, CTS, routing, IR drop, and EM/antenna analysis
- Tcl, Python, or Perl scripting ability for flow automation and debugging
Responsibilities
- Own end-to-end block-level and subsystem physical design, including floorplanning, synthesis, placement, clock tree synthesis, routing, and GDSII
- Drive timing closure across corners and modes, including constraint development, STA debugging, and ECO implementation
- Close sign-off for electromigration, IR drop, RC extraction, correlation, and physical verification
- Generate abstracts, views, and timing budgets for hierarchical top-level integration
- Collaborate with RTL designers and provide physical-design feedback to improve PPA
- Improve the PPA of owned blocks and contribute learnings to the RTL-to-GDSII flow
- Supervise outsourced physical-design work and ensure delivered blocks meet quality and closure requirements
Benefits
- Medical, dental, and vision coverage
- USD 500 monthly credit for waiving medical benefits
- USD 2,500 monthly housing subsidy for employees living within walking distance of the office
- Relocation support to San Jose
- Wellness benefits covering fitness and mental health
- Daily office lunch and dinner
- Unlimited compute budget subject to ROI justification