Physical Design Engineer Block Level Subsystem Implementation

Skills

About the Role

You will own end-to-end block and subsystem physical design, from synthesis through GDSII sign-off. You will drive timing and signoff closure, optimize power, performance, and area, create integration collateral, collaborate with RTL designers, and oversee outsourced physical-design deliverables.

Requirements

• 5–10+ years of physical-design experience
• Knowledge of RTL-synthesis-to-GDSII tools, flows, and methodology
• Experience with backend design and timing closure on 5 nm or smaller process nodes
• Experience with Cadence Innovus and Genus or Synopsys Fusion Compiler
• Experience with signoff tools including PrimeTime, Tempus, or Voltus
• Experience with UPF low-power methodology, power verification, synthesis, scan insertion, ATPG, formal verification, floorplanning, placement, CTS, routing, IR-drop analysis, and EM or antenna analysis
• Tcl, Python, or Perl scripting ability

Responsibilities

• Own end-to-end block and subsystem physical design from floorplanning through GDSII
• Drive timing closure, constraint development, STA debug, and ECO implementation
• Close signoff across EM, IR drop, RC extraction, and physical verification
• Generate abstracts, views, and timing budgets for hierarchical integration
• Provide physical-design feedback to RTL designers to improve PPA
• Improve block PPA and contribute learnings to the RTL-to-GDSII flow
• Supervise outsourced physical-design work and ensure delivered-block quality and closure

Benefits

• Medical, dental, and vision coverage with generous premium coverage
• USD 500 monthly credit for waiving medical benefits
• Wellness benefits for fitness and mental health
• Daily office lunch and dinner
• Unlimited compute budget subject to ROI justification