Senior RTL Engineer
Velaura AI develops ultra-low-power silicon and software technologies for AI compute infrastructure.
Funding history
About Velaura AI, Inc.
Velaura AI is an AI compute infrastructure company developing ultra-low-power silicon and software technologies. Its Titan Core™ platform uses proprietary digital chip IP, low-voltage libraries, EDA flows, and design methodologies to improve performance per watt in AI accelerators while maintaining performance, yield, and reliability. The company also applies this technology to Physical AI systems, including industrial robots, autonomous machines, drones, humanoids, and edge devices. Velaura engages hyperscalers, XPU companies, and developers of next-generation AI infrastructure and Physical AI solutions.
Skills
Candidate Availability
Required and preferred rules are kept separate and reflect the wording in the original posting.
About the Role
You will own RTL design, implementation, and optimization for important SoC areas. You will develop microarchitectures, work with software on hardware interfaces and execution flows, improve compute, memory, interconnect, DMA, and power-management logic, analyze bottlenecks, mentor engineers, and lead design reviews.
Requirements
- 8+ years of RTL design experience for complex digital systems with ownership through tapeout
- Understanding of computer architecture, microarchitecture, and digital design
- Expert Verilog and SystemVerilog skills
- Experience with lint, CDC, synthesis-aware coding, and low-power intent
- Knowledge of performance, power, and area tradeoffs and data-driven microarchitecture decisions
- Understanding of memory systems, interconnects, caches, DMA engines, or accelerator architectures
- Experience with hardware and software co-design and system-level performance optimization
- Debugging and problem-solving skills
- Ability to technically lead in a multidisciplinary engineering environment
Responsibilities
- Own RTL design, implementation, and optimization for key SoC areas
- Develop efficient microarchitectures and drive decisions within areas of ownership
- Participate in hardware and software co-design across AI workloads, memory systems, runtime software, and system architecture
- Define hardware interfaces, execution flows, memory hierarchies, and performance-critical interactions with software teams
- Contribute to compute engines, memory subsystems, interconnect fabrics, control processors, DMA engines, and power-management logic
- Optimize designs for performance, power, area, scalability, and reliability
- Partner with verification and physical design teams and mentor junior engineers
- Analyze performance bottlenecks and propose architectural and implementation improvements
- Use AI-assisted development workflows to improve productivity, quality, and design exploration
- Participate in and lead design reviews
Benefits
- Equity compensation
- Medical coverage
- Dental coverage
- Vision coverage
- Paid time off
- Flexible work arrangements