SoC Subsystem Design Engineer
South Korean AI semiconductor and infrastructure company building inference accelerators, servers, racks, and software for production-scale AI deployment.
Funding history
Investors
About Rebellions
Rebellions develops purpose-built AI inference hardware and an accompanying software stack. Its current offerings include the Rebel100 accelerator and deployable RebelServer, RebelRack, and RebelPOD systems, designed for energy-efficient data-center inference.
Skills
Candidate Availability
Required and preferred rules are kept separate and reflect the wording in the original posting.
About the Role
You will define SoC or subsystem architecture, create RTL designs, and integrate high-performance AI accelerator systems. You will coordinate IP integration with verification, software, and backend functions, work with DSP engineers, and lead silicon bring-up and hardware-software debugging. You will apply clock and power-control methods to improve robustness.
Requirements
- At least 10 years of experience in high-complexity RTL design using SystemVerilog or Verilog
- Experience leading SoC subsystem designs from conceptual architecture through physical implementation
- Expertise with VCS or Xcelium for RTL and gate-level simulation debugging
- Mastery of Lint, CDC, RDC, DFT, synthesis, and IP-XACT integration flows
- Understanding of the full SoC lifecycle, including power-on reset sequences and clock-domain crossing
Responsibilities
- Lead SoC or subsystem architecture, RTL design, and system integration
- Coordinate IP integration with verification, software, and backend functions
- Collaborate with DSP engineers on hardware implementation of algorithms
- Lead silicon bring-up and hardware-software debugging
- Apply clock and power-control design methods to improve SoC robustness
Hiring Process
Document screening → online interview → onsite interview → culture-fit interview → compensation discussion → final acceptance