Principal Design for Test Engineer

Skills

About the Role

You will own DFT and DFx strategy from architecture through tapeout and first silicon. You will define DFT architecture and standards, implement scan and test infrastructure, integrate DFT into RTL and third-party IP, and lead pre-silicon verification and signoff. You will guide physical implementation, oversee external DFT work, resolve issues, and partner across chip-development functions.

Requirements

• BS, MS, or PhD in Electrical Engineering or Computer Engineering
• 12+ years of ASIC development experience
• Hands-on DFT implementation experience on complex SoCs with successful production tapeouts
• Knowledge of scan architectures, ATPG, memory BIST, logic BIST, boundary scan, IJTAG, test compression, fault models, and structural coverage analysis
• Experience with Siemens Tessent, Synopsys TestMAX DFT, Cadence Modus, or equivalent DFT tools
• RTL skills using Verilog/SystemVerilog
• Experience with synthesis and gate-level verification
• Python, Tcl, Perl, or similar scripting skills
• Debugging experience across RTL, netlists, and silicon test
• Ability to drive technical execution across cross-functional engineering teams
• Authorization to work in the U.S.

Responsibilities

• Define and maintain DFT architecture for current and future ASIC generations
• Develop DFT and DFx roadmaps, standards, review processes, signoff criteria, and best practices
• Architect and implement scan insertion, compression, ATPG, memory BIST, logic BIST, boundary scan, IJTAG, and debug features
• Integrate DFT into internal RTL and third-party IP
• Develop DFT verification plans and validate DFT functionality through simulation and gate-level verification
• Ensure structural coverage targets and ATPG strategies are achieved before tapeout
• Own DFT signoff
• Guide scan-chain partitioning, compression planning, test-clock architecture, and test-mode integration
• Lead and review external DFT execution and resolve issues
• Partner across RTL, design verification, physical design, package and test engineering, firmware, software, and silicon validation

Benefits

• Equity
• Company-paid medical, dental, and vision insurance for employees and dependents
• Company-paid life and disability coverage
• Supplemental hospital, critical illness, and accident coverage
• Unlimited paid time off
• 13 paid company holidays
• Company-provided computer and home office setup
• 401(k) with company matching from day one
• H-1B visa transfer facilitation for eligible candidates