Staff Analog Design Engineer SerDes Clocking

Skills

About the Role

You will own transistor-level clocking designs for high-speed SerDes links, from specification through silicon characterization. You will develop PLL, CDR, phase-interpolation, clock-distribution, verification, layout, and silicon bring-up solutions.

Requirements

• BS, MS, or PhD in Electrical Engineering
• 5+ years of hands-on analog and mixed-signal circuit design experience
• Experience owning a low-jitter PLL, phase interpolator, or CDR loop through silicon
• Knowledge of PLL architecture, loop dynamics, VCO design, phase noise theory, and CDR architectures
• Experience with jitter decomposition and budgeting
• Experience with FinFET or GAA process nodes
• Experience with Cadence Virtuoso, Spectre, Monte Carlo analysis, corner analysis, and post-layout simulation
• Silicon bring-up and bench-debug experience with phase-noise analyzers, high-speed scopes, and BERTs

Responsibilities

• Design low-jitter frequency-synthesis circuits including PLLs, loop filters, VCOs, and divider chains
• Own phase-interpolator and phase-rotation designs
• Design high-frequency clock distribution and skew-control circuitry
• Define and verify CDR architecture and loop dynamics
• Build phase-noise and jitter budgets
• Develop verification environments and behavioral models
• Drive physical layout for clocking blocks
• Perform silicon bring-up and bench characterization

Benefits

• Equity
• Bonus
• Medical insurance
• Dental insurance
• Vision insurance
• 401(k)