SoC Clock Reset and Peripheral Architecture Engineer
South Korean AI semiconductor and infrastructure company building inference accelerators, servers, racks, and software for production-scale AI deployment.
Funding history
Investors
About Rebellions
Rebellions develops purpose-built AI inference hardware and an accompanying software stack. Its current offerings include the Rebel100 accelerator and deployable RebelServer, RebelRack, and RebelPOD systems, designed for energy-efficient data-center inference.
Skills
Candidate Availability
Required and preferred rules are kept separate and reflect the wording in the original posting.
About the Role
You will define system and SoC-level clocking, reset, peripheral, and GPIO architectures. You will account for chiplet, package, board, power-domain, clock-domain, and reset-domain requirements, align power-state and DVFS strategies, and guide design exploration.
Requirements
- Master’s degree or higher in Electrical Engineering, Computer Science, or a related field
- 5+ years of experience in SoC and system architecture
- Comprehensive understanding of SoC design, clocking and reset principles, power, clock, and reset domain interactions, and peripheral and GPIO subsystem design
Responsibilities
- Define system- and SoC-level clocking and reset architecture
- Architect peripheral and GPIO subsystems for diverse system use cases and physical configurations
- Ensure architectural consistency across SoC, package, and board boundaries
- Align clock and reset architecture with power states and DVFS strategies
- Provide architectural guidance during design exploration
Hiring Process
Resume screening > online interview > onsite interview > culture-fit interview > compensation discussion > final offer