Power Management Architect
Velaura AI develops ultra-low-power silicon and software technologies for AI compute infrastructure.
Funding history
About Velaura AI, Inc.
Velaura AI is an AI compute infrastructure company developing ultra-low-power silicon and software technologies. Its Titan Core™ platform uses proprietary digital chip IP, low-voltage libraries, EDA flows, and design methodologies to improve performance per watt in AI accelerators while maintaining performance, yield, and reliability. The company also applies this technology to Physical AI systems, including industrial robots, autonomous machines, drones, humanoids, and edge devices. Velaura engages hyperscalers, XPU companies, and developers of next-generation AI infrastructure and Physical AI solutions.
Skills
Candidate Availability
Required and preferred rules are kept separate and reflect the wording in the original posting.
About the Role
You will own the power architecture for Physical AI SoCs from early architecture through tape-out and production. You will define power domains, DVFS strategies, power states, delivery networks, and power-management controls. You will model power budgets, drive PPA trade-offs, validate low-power intent, and establish power architecture standards and review practices.
Requirements
- 8+ years of experience in power management, mixed-signal, or SoC architecture
- Expertise in low-power design techniques, including power domains, DVFS, clock and power gating, adaptive voltage scaling, retention, and power-state management
- Understanding of power delivery networks, PMICs, voltage regulation, and power, thermal, and package constraints
- Experience with power intent and low-power methodology, including UPF or CPF
- Experience with power modeling and analysis across the SoC design flow
- Experience defining and validating power-management policies across silicon design, firmware, and platform software
- Bachelor’s or advanced degree in Electrical or Computer Engineering or a related field, or equivalent practical experience
- Written and verbal communication
- Technical leadership
- Mentoring
Responsibilities
- Own the SoC power architecture, including power domains, DVFS strategy, power states, and power delivery networks
- Define dynamic and static power-management techniques, including clock and power gating, adaptive voltage scaling, body biasing, and retention strategies
- Establish power and energy budgets and drive power, performance, and area trade-offs
- Architect on-die power-management controls, including PMIC interfaces, controllers, sensors, telemetry, and software policies
- Embed power intent into the design flow and validate it through implementation and silicon bring-up
- Define power and thermal management strategies, including thermal throttling, energy-aware scheduling, and safe operating limits
- Establish power architecture standards, modeling methodology, and review practices
- Mentor engineers
Benefits
- Equity compensation
- Medical coverage
- Dental coverage
- Vision coverage
- Paid time off
- Flexible work arrangements