Senior Staff Physical Design Engineer

Skills

About the Role

You will implement complex digital blocks in advanced process nodes from synthesis through physical verification. You will drive full-chip timing signoff, power analysis and optimization, floorplanning, IO placement, clock distribution, DRC/LVS cleanup, and functional and timing ECOs. You will also resolve EDA tool issues and automate or customize flows with scripts.

Requirements

• Bachelor’s degree in Electrical Engineering or Computer Engineering
• 12+ years of industry experience as a Physical Design Engineer
• Experience completing block-level or top-level physical design for large taped-out ASICs or mixed-signal chips
• Knowledge of timing closure and LVS/DRC closure
• Experience with TCL and Python or other scripting languages
• Teamwork and cross-functional collaboration skills
• Ability to thrive in a fast-paced environment

Responsibilities

• Implement digital blocks from synthesis through physical verification
• Drive full-chip STA signoff, review constraints, debug timing reports, and implement ECOs
• Drive power analysis and optimization while balancing area and performance
• Drive full-chip floorplanning, IO placement, and clock distribution
• Customize clock implementation for functional and test clocks
• Debug and clean up DRC/LVS
• Implement functional and timing ECOs
• Work with EDA companies to resolve tool issues
• Write TCL, Python, or Shell scripts to automate or customize flows

Benefits

• Comprehensive medical, dental, and vision health plan
• Retirement savings matching program
• Basic, voluntary, and AD&D life insurance
• Vacation, sick time, and public holidays
• Paid family leave
• Short-term and long-term disability coverage
• Commuter benefits
• Flexible hybrid workplace model
• Equity grants for eligible full-time employees