Senior Staff PCB Design Engineer

Skills

About the Role

You will lead the physical layout of high-complexity AI accelerator cards and system baseboards. You will define routing constraints, automate layout workflows, execute ultra-high-speed interface layouts, develop PCB stack-ups, and work with power engineers, fabricators, and manufacturing partners to support production.

Requirements

• BS in Electrical/Electronic Engineering or equivalent practical experience
• 10+ years of experience in high-speed, high-density PCB layout for servers, networking, or AI accelerators
• Proficiency in Cadence Allegro Constraint Manager
• Ability to write and deploy SKILL scripts or use the Allegro API
• Understanding of high-speed routing techniques and HDI/ELIC design
• Track record routing 112G SerDes and complex DDR5/HBM interfaces
• Experience establishing a Library Management System and standardized footprint/padstack processes
• Familiarity with PLM/PDM integration for layout releases and ECO workflows
• Knowledge of PCB warpage mitigation strategies for large-form-factor ASICs and MCMs

Responsibilities

• Lead full-cycle layout for high-complexity AI accelerator cards and system baseboards
• Architect and manage the Cadence Allegro Constraint Manager hierarchy
• Develop automation scripts for layout tasks, DRC checks, and reporting
• Execute layouts for PCIe Gen5/6, CXL, and die-to-die interconnects
• Partner on PDN strategy, VRM layouts, and decoupling capacitor placement
• Drive PCB stack-up definition using advanced low-loss materials and hybrid build-ups
• Interface with fabricators and contract manufacturers to meet DFM, DFT, and DFA requirements

Benefits

• Medical insurance
• Dental insurance
• Vision insurance
• 401k
• Equity
• Bonus
• Incentive opportunities