Senior Formal Verification Engineer
Velaura AI develops ultra-low-power silicon and software technologies for AI compute infrastructure.
Funding history
About Velaura AI, Inc.
Velaura AI is an AI compute infrastructure company developing ultra-low-power silicon and software technologies. Its Titan Core™ platform uses proprietary digital chip IP, low-voltage libraries, EDA flows, and design methodologies to improve performance per watt in AI accelerators while maintaining performance, yield, and reliability. The company also applies this technology to Physical AI systems, including industrial robots, autonomous machines, drones, humanoids, and edge devices. Velaura engages hyperscalers, XPU companies, and developers of next-generation AI infrastructure and Physical AI solutions.
Skills
Candidate Availability
Required and preferred rules are kept separate and reflect the wording in the original posting.
About the Role
You will define and scale formal verification for complex SoC blocks. You will create properties and formal testbenches, close proofs, debug counterexamples, verify arithmetic behavior, build reusable formal applications, integrate formal coverage into signoff, and maintain automated regression infrastructure.
Requirements
- 10+ years in functional verification with substantial formal verification experience
- CPU, processor, floating-point, arithmetic datapath, or vector/SIMD verification
- SystemVerilog Assertions
- Formal property development
- JasperGold, VC Formal, or Questa Formal / OneSpin
- Constraint development
- Computer architecture
- Microarchitecture
- SoC design
- Floating-point arithmetic
- IEEE-754
- Scripting
- Build automation
- Regression pipelines
- CI pipelines
Responsibilities
- Own and drive formal verification for complex SoC blocks
- Write SVA properties and formal testbenches for functional correctness
- Apply full proofs, bounded model checking, assume-guarantee reasoning, and abstraction
- Debug counterexamples and converge hard proofs
- Verify floating-point and arithmetic units for IEEE-754 compliance
- Build reusable formal applications for connectivity, registers, deadlock, liveness, X-propagation, and control paths
- Define constraints and modeling assumptions and prove their consistency
- Drive formal coverage closure and integrate it into verification signoff
- Align formal and simulation verification plans with architects, RTL, and simulation teams
- Maintain automation, scripting, CI hooks, formal regressions, and proof tracking
Benefits
- Competitive equity compensation
- Medical coverage
- Dental coverage
- Vision coverage
- Paid time off
- Flexible work arrangements