Formal Verification Engineer

Etched is an AI-hardware company building rack-scale frontier inference clusters.

San Jose, United States
About Etched

Etched co-designs chips, racks, software, and manufacturing systems for efficient inference of frontier AI models, targeting throughput, latency, cost, and power efficiency across prefill and decode workloads.

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Skills

Candidate Availability

Required and preferred rules are kept separate and reflect the wording in the original posting.

About the Role

You will define formal verification strategy and plans for complex ASIC IP, interfaces, and SoC integration. You will create reusable formal environments, drive proof convergence and sign-off, debug RTL and protocol issues, and align formal work with simulation, emulation, software, and firmware verification.

Requirements

  • 5+ years of design verification experience with significant hands-on formal verification experience
  • Proficiency with SystemVerilog, SystemVerilog Assertions, and formal verification methodology
  • Experience with Cadence JasperGold, Synopsys VC Formal, or Siemens Questa Formal
  • Understanding of digital design, computer architecture, datapaths, interconnects, memory systems, and standard SoC interfaces
  • Ability to model complex design behavior using assumptions, abstractions, constraints, cut-points, checkers, and reference models
  • Debugging skills across RTL, specifications, formal counterexamples, simulation waveforms, and verification reports
  • Experience collaborating with architecture, RTL, UVM DV, emulation, software, firmware, and vendor teams

Responsibilities

  • Define and drive formal verification strategy
  • Develop formal verification plans
  • Build reusable formal verification environments
  • Drive proof convergence and formal sign-off confidence
  • Translate specifications into formal properties and closure criteria
  • Align formal verification with simulation, coverage, regressions, and bring-up
  • Debug RTL, protocol, datapath, connectivity, and integration bugs
  • Contribute to formal methodology, regression automation, reporting, and best practices

Benefits

  • Medical, dental, and vision coverage
  • $500 per month credit for waiving medical benefits
  • $2.5k per month housing subsidy for eligible employees
  • Relocation support
  • Wellness benefits
  • Daily lunch and dinner in the office
Formal Verification Engineer at Etched | JobStash