RTL Lead – Physical AI Compute
Velaura AI develops ultra-low-power silicon and software technologies for AI compute infrastructure. Its solutions serve hyperscale data centers and Physical AI applications such as robotics, autonomous systems, drones, and edge devices.
Maintainer signals as of 8/23/2026
Funding history
About Velaura AI, Inc.
Velaura AI is an AI compute infrastructure company developing ultra-low-power silicon and software technologies. Its Titan Core™ platform uses proprietary digital chip IP, low-voltage libraries, EDA flows, and design methodologies to improve performance per watt in AI accelerators while maintaining performance, yield, and reliability. The company also applies this technology to Physical AI systems, including industrial robots, autonomous machines, drones, humanoids, and edge devices. Velaura engages hyperscalers, XPU companies, and developers of next-generation AI infrastructure and Physical AI solutions.
Skills
Candidate Availability
Required and preferred rules are kept separate and reflect the wording in the original posting.
About the Role
Lead RTL development for key portions of a Physical AI SoC, translate system requirements into microarchitectures, drive hardware/software co-design, make performance and power decisions, review RTL, establish engineering methodologies, and mentor RTL engineers.
Requirements
- Strong RTL design experience in complex SoCs or related systems
- Deep understanding of digital design fundamentals and microarchitecture
- Experience with Verilog and SystemVerilog
- Familiarity with memory systems, interconnect fabrics, cache hierarchies, and system-level data movement
- Experience balancing performance, power, area, and design complexity
- Ability to drive technical projects from concept through silicon bring-up
- Experience with hardware/software co-design and system-level performance optimization
Responsibilities
- Lead RTL development across key SoC components
- Translate system requirements into robust microarchitectures
- Drive hardware/software co-design across AI workloads, memory systems, runtime software, and system architecture
- Define programming models, execution flows, memory hierarchies, and performance-critical interfaces
- Drive design decisions across compute engines, memory subsystems, interconnect, control logic, and system infrastructure
- Conduct architecture and RTL reviews
- Establish engineering processes and design methodologies
- Mentor and develop RTL engineers
Benefits
- Performance-based incentives
- Equity participation
- Medical coverage
- Dental coverage
- Vision coverage
- Paid time off
- Flexible work arrangements