RTL Engineer

Skills

About the Role

You will design and implement a die-to-die interconnect subsystem, define its microarchitecture with an architect, integrate controller and PHY IP, and collaborate with verification, SoC integration, firmware, and PSI functions. You will also support link bring-up and post-silicon debugging.

Requirements

• 6+ years of combined RTL-design experience using SystemVerilog or Verilog, or fewer years with clear interconnect or link-layer RTL depth.
• End-to-end ownership of a non-trivial RTL block.
• Logic simulation and RTL root-cause debugging skills using VCS or Xcelium.
• Knowledge of Lint, CDC, and synthesis flows.
• Cross-functional collaboration skills.
• Experience with tape-out and post-silicon debug.
• Knowledge of AMBA, AXI, ACE, CHI, or packetized on-chip protocols.
• Knowledge of clock-domain crossing, reset-domain crossing, and power or clock gating.
• Knowledge of scan insertion, compression, and DFT-aware RTL practices.
• Understanding of SerDes-based high-speed links and PHY interfaces.

Responsibilities

• Design and implement the die-to-die interconnect subsystem.
• Implement transaction management, datapaths, link reliability, test, debug, and monitoring structures.
• Define interconnect microarchitecture with the architect.
• Design against UCIe, CHI, and related standards.
• Integrate vendor controller and PHY IP through standard interfaces.
• Collaborate with verification, SoC integration, firmware, and PSI functions.
• Participate in link bring-up and post-silicon debugging.

Hiring Process

Application review → online interview → onsite interview → culture-fit interview → compensation discussion → final decision.