RTL Engineer Memory Subsystem
Velaura AI develops ultra-low-power silicon and software technologies for AI compute infrastructure.
Maintainer signals as of 9/2/2026
Funding history
About Velaura AI, Inc.
Velaura AI is an AI compute infrastructure company developing ultra-low-power silicon and software technologies. Its Titan Core™ platform uses proprietary digital chip IP, low-voltage libraries, EDA flows, and design methodologies to improve performance per watt in AI accelerators while maintaining performance, yield, and reliability. The company also applies this technology to Physical AI systems, including industrial robots, autonomous machines, drones, humanoids, and edge devices. Velaura engages hyperscalers, XPU companies, and developers of next-generation AI infrastructure and Physical AI solutions.
Skills
Candidate Availability
Required and preferred rules are kept separate and reflect the wording in the original posting.
About the Role
You will design and optimize RTL for the SoC memory subsystem, including memory controllers, fabric interfaces, and external memory PHY integration. You will drive high-speed, low-power memory-path design, collaborate on hardware interfaces and performance analysis, and optimize performance, power, area, scalability, reliability, and silicon bring-up.
Requirements
- Experience designing RTL for complex digital systems and memory subsystem blocks
- Experience integrating memory controllers with memory PHYs, including DFI, initialization, training, and bring-up
- Knowledge of LPDDR4, LPDDR4X, LPDDR5, LPDDR5X, DDR, or HBM technologies
- Knowledge of computer architecture, microarchitecture, and digital design
- Verilog and SystemVerilog skills
- Knowledge of RTL design methodologies, lint, clock-domain crossing analysis, synthesis-aware coding, and low-power intent
- Knowledge of performance, power, and area tradeoffs in memory paths
- Debugging and problem-solving skills
Responsibilities
- Design, implement, and optimize RTL for memory controllers, fabric interfaces, and external memory PHY integration
- Own memory-controller and PHY integration, including DFI interfaces, initialization, training, calibration, and bring-up hooks
- Drive high-speed, low-power memory-path design, timing closure, power-state management, clock and power gating, and DVFS interactions
- Define hardware interfaces, memory maps, execution flows, scheduling, prefetching, and quality-of-service interactions
- Analyze bandwidth, latency, and utilization bottlenecks and propose improvements
- Optimize designs for performance, power, area, scalability, reliability, ECC, and error reporting
- Partner with verification, physical design, memory IP, and PHY vendors during development and silicon bring-up
- Use AI-assisted development workflows for productivity, quality, and design exploration
- Participate in design reviews
Benefits
- Equity compensation
- Medical coverage
- Dental coverage
- Vision coverage
- Paid time off
- Flexible work arrangements