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Principal Debug Validation Engineer

G
Graphcore

Graphcore is a Bristol-based AI chipmaker (IPU accelerators), a SoftBank subsidiary and a Molten Ventures portfolio company.

0 current maintainers0 active leads1 lead step-down1 early lead departureTeam intelligence

Maintainer signals as of 8/20/2026

About Graphcore

Graphcore (graphcore.ai) is a British semiconductor company building Intelligence Processing Units (IPUs) for AI workloads. Founded in Bristol in 2016, it was acquired by SoftBank in 2024. It is a portfolio company of Molten Ventures.

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Skills

Candidate Availability

Required and preferred rules are kept separate and reflect the wording in the original posting.

About the Role

You will lead post-silicon debug and validation activities for AI compute silicon and platform technologies. You will investigate complex silicon firmware software and system-level issues, develop debug methodologies, analyze logs and hardware data, build automated validation infrastructure, support testing and diagnostics, communicate technical risks, and contribute to readiness and product quality decisions.

Requirements

  • Strong experience in bare metal environments
  • Knowledge of SoC and platform architectures
  • Expertise in debug infrastructure and post-silicon debug methodologies
  • Strong programming skills in Python C or CMM
  • Experience with post-silicon validation in digital ASIC environments
  • Strong Linux and Python experience
  • Deep knowledge of scan DFT JTAG and trace infrastructure
  • Debug skills including fault tree analysis failure isolation fishbone methodologies and system-level debug techniques
  • Ability to work independently across hardware firmware and software domains
  • Understanding of DFT flows from insertion through post-silicon validation
  • Experience developing tooling for parsing and analyzing debug data including scan dump parsing
  • Driver-level experience with PCIe Ethernet LPDDR DDR HBM I2C I3C or SPI
  • Experience with CoreSight CTI ETx DStream JLink Lauterbach ATB or STM
  • Knowledge of mixed-signal building blocks including PLLs high-speed PHYs and IC control and communication protocols
  • Experience with Arm CPU architectures system IP and associated debug tooling
  • Experience with AMBA protocols
  • Understanding of ML applications and associated workloads
  • Experience in characterization failure analysis test development statistical analysis and customer support

Responsibilities

  • Lead post-silicon debug and validation activities for AI compute silicon and platform technologies
  • Drive prioritization planning and execution across multiple projects and milestones
  • Investigate and resolve complex silicon firmware software and system-level issues
  • Develop structured debug methodologies and failure analysis processes
  • Collaborate with architecture RTL firmware software and systems engineering teams to identify root causes
  • Drive debug of CPU memory interconnect and high-speed I/O subsystems
  • Develop and enhance automated debug regression and validation infrastructure using Python
  • Analyze logs traces telemetry and hardware data
  • Support validation tests debug tooling and custom diagnostics
  • Define validation metrics debug workflows and reporting standards
  • Drive continuous improvement of debug processes validation methodologies and engineering workflows
  • Communicate technical risks status and recommendations to engineering leadership and stakeholders
  • Support silicon readiness reviews and product quality and release decisions