STA / Synthesis Engineer

Skills

About the Role

You own RTL-to-gate synthesis, static timing analysis, and timing closure for AI and high-performance computing silicon. You develop constraints, optimize timing, power, area, and cost, lead sign-off and ECO flows, improve synthesis and timing methodologies, automate workflows, and collaborate across implementation and verification disciplines.

Requirements

• 5–15 years of hands-on experience in ASIC/SoC implementation, synthesis, STA, and timing closure
• Experience with RTL-to-gate synthesis and timing closure for complex digital designs
• Experience with compute, CPU, VPU, AI accelerator, SoC, or high-performance digital IP designs
• Expertise in industry-standard synthesis and STA tools from Synopsys and Cadence
• Understanding of multi-mode multi-corner timing analysis, constraint development, timing debug, and sign-off methodology
• Experience with hierarchical, block-level, subsystem-level, and full-chip timing closure
• Experience with advanced process technologies including 2nm or 3nm nodes
• Understanding of low-power design, clock gating, multi-voltage domains, and power-aware implementation
• Experience with UPF/CPF-based power intent and power-aware synthesis
• Experience with timing, functional, and late-stage ECO flows
• Scripting skills in Tcl, Perl, or Python

Responsibilities

• Drive RTL-to-gate synthesis for compute, CPU, VPU, AI accelerator, and low-power cores
• Own synthesis setup, constraints, optimization, quality checks, and netlist delivery
• Lead static timing analysis and timing closure across modes, corners, voltage domains, and clock domains
• Optimize designs for timing, power, area, and cost
• Develop and validate timing constraints
• Drive multi-mode multi-corner timing analysis and convergence
• Resolve timing, constraints, clocking, reset, DFT, and low-power implementation issues
• Own timing sign-off readiness
• Drive hierarchical timing closure
• Implement low-power design strategies and power intent flows
• Execute timing ECO flows
• Support physical-aware synthesis and placement-aware optimization
• Improve synthesis, STA, constraints, ECO, and timing closure methodologies
• Evaluate and deploy EDA tools and automation
• Develop scripts for synthesis, STA, reporting, debug, and flow validation
• Provide technical leadership across implementation and sign-off

Benefits

• Performance-based incentives
• Equity participation
• Medical coverage
• Dental coverage
• Vision coverage
• Paid time off
• Flexible work arrangements
• Professional development opportunities