Design Verification Engineer – CPU
Velaura AI develops ultra-low-power silicon and software technologies for AI compute infrastructure. Its solutions serve hyperscale data centers and Physical AI applications such as robotics, autonomous systems, drones, and edge devices.
Maintainer signals as of 8/23/2026
Funding history
About Velaura AI, Inc.
Velaura AI is an AI compute infrastructure company developing ultra-low-power silicon and software technologies. Its Titan Core™ platform uses proprietary digital chip IP, low-voltage libraries, EDA flows, and design methodologies to improve performance per watt in AI accelerators while maintaining performance, yield, and reliability. The company also applies this technology to Physical AI systems, including industrial robots, autonomous machines, drones, humanoids, and edge devices. Velaura engages hyperscalers, XPU companies, and developers of next-generation AI infrastructure and Physical AI solutions.
Skills
Candidate Availability
Required and preferred rules are kept separate and reflect the wording in the original posting.
About the Role
You will own verification for custom CPU units such as instruction fetch, decode, load-store logic, and multiple cache levels. You will create test and coverage plans, build portable verification environments, develop instruction-level stimulus, compare results with a golden instruction set simulator, verify architectural behavior, execute regressions, and support emulation, FPGA prototyping, and pre-silicon software bring-up.
Requirements
- 8 or more years verifying high-performance CPUs or complex digital designs
- Have strong computer architecture and microarchitecture fundamentals
- Have experience with SystemVerilog UVM C C++ assertions and coverage-driven verification
- Own design verification from test planning through coverage closure
- Have experience writing test plans portable testbenches and transactors
- Have experience debugging issues across hardware and software boundaries
- Hold a BS or higher in Computer Engineering Electrical Engineering or Computer Science
- Work effectively in a collaborative multidisciplinary engineering environment
- Knowledge of ARM or RISC-V instruction sets cache coherence memory ordering prefetching branch prediction speculative execution or address translation is preferred
Responsibilities
- Own verification of custom CPU units including instruction fetch decode load-store logic and caches
- Translate microarchitecture intent into detailed test and coverage plans
- Build portable SystemVerilog and UVM verification environments with stimulus checkers assertions trackers and coverage
- Develop instruction-level stimulus and compare results against a golden instruction set simulator
- Verify memory ordering coherence exceptions and privilege behavior
- Verify latency bandwidth and cache behavior under representative workloads
- Execute regressions and track bug and coverage metrics
- Support emulation FPGA prototyping and pre-silicon software bring-up and drive root-cause analysis
Benefits
- Performance-based incentives
- Equity participation
- Medical coverage
- Dental coverage
- Vision coverage
- Paid time off
- Flexible work arrangements