Custom Circuit Design (Sr. Staff / Principal)
Velaura AI develops ultra-low-power silicon and software technologies for AI compute infrastructure. Its solutions serve hyperscale data centers and Physical AI applications such as robotics, autonomous systems, drones, and edge devices.
Maintainer signals as of 8/23/2026
Funding history
About Velaura AI, Inc.
Velaura AI is an AI compute infrastructure company developing ultra-low-power silicon and software technologies. Its Titan Core™ platform uses proprietary digital chip IP, low-voltage libraries, EDA flows, and design methodologies to improve performance per watt in AI accelerators while maintaining performance, yield, and reliability. The company also applies this technology to Physical AI systems, including industrial robots, autonomous machines, drones, humanoids, and edge devices. Velaura engages hyperscalers, XPU companies, and developers of next-generation AI infrastructure and Physical AI solutions.
Skills
Candidate Availability
Required and preferred rules are kept separate and reflect the wording in the original posting.
About the Role
Velaura seeks a Sr. Staff/Principal Custom Circuit Design Engineer to lead high-performance, low-power standard-cell libraries and custom digital circuits across advanced process technologies. The role covers transistor-level innovation, arithmetic circuits, verification, reliability sign-off, methodology improvements, cross-functional collaboration, and mentoring.
Requirements
- 10+ years of experience in custom digital circuit design, standard-cell development, or memory circuit design.
- Expertise in transistor-level CMOS design for advanced technology nodes.
- Experience designing and optimizing high-performance, low-power standard-cell libraries.
- Understanding of FinFET and Gate-All-Around technologies.
- Experience with HSPICE, PrimeSim XA, or Spectre.
- Experience with StarRC or Quantus parasitic extraction.
- Knowledge of statistical verification, Monte Carlo analysis, and variation-aware design.
- Experience with reliability verification including EM, IR-drop, aging, and self-heating.
- Master's or Ph.D. in Electrical Engineering, Electronics Engineering, or a related discipline preferred.
- Experience with Python, Tcl, or Perl automation preferred.
Responsibilities
- Lead standard-cell architecture, design, and optimization for performance, power, and area.
- Design and optimize transistor-level sequential and combinational circuits.
- Architect arithmetic building blocks including adders, multipliers, and integer and floating-point MAC units.
- Develop schematics in Cadence Virtuoso and perform parasitic extraction using StarRC or Quantus.
- Verify circuits across PVT corners using HSPICE, PrimeSim XA, or Spectre.
- Drive Monte Carlo statistical verification and variation analysis.
- Own reliability sign-off including electromigration, IR-drop, self-heating, aging, ESD, and latch-up robustness.
- Drive low-power circuit innovations and power-intent-aware methodologies.
- Collaborate with layout, characterization, physical design, CAD, STA, and product engineering teams.
- Improve design methodologies, automation, and technical best practices.
- Mentor engineers and provide technical leadership.
Benefits
- Performance-based incentives
- Equity participation
- Medical coverage
- Dental coverage
- Vision coverage
- Paid time off
- Flexible work arrangements
- Professional development opportunities
Hiring Process
The company may use AI tools to review applications, analyze resumes, assess responses, and identify inconsistencies or verification signals. These tools assist the recruitment team; final hiring decisions are made by humans.