AI Silicon Physical Design Engineer
53 minutes agoHeadSalary: 150K - 250KSunnyvale, USAOnsiteFull TimeEngineeringJobs by Cerebras Systems, Inc.
Cerebras Systems, Inc.Visit Cerebras Systems, Inc. website
Cerebras builds wafer-scale AI computing systems and a cloud inference platform for training, fine-tuning, and serving AI models.
Sunnyvale, California, United States
About Cerebras Systems, Inc.
Cerebras Systems is an AI-infrastructure company founded in 2015. It sells rack-scale wafer-scale computing systems and provides cloud-based, API-accessible AI inference alongside on-premises deployments.
Skills
Candidate Availability
Required and preferred rules are kept separate and reflect the wording in the original posting.
About the Role
You will synthesize, place, and route high-speed designs and integrate physical-design blocks into full-chip architecture. You will drive timing closure, physical verification, power-performance-area optimization, IR/EM analysis, floorplanning, and design-flow improvements with RTL engineers.
Requirements
- 10+ years of physical design and physical verification experience
- Knowledge of block-level and full-chip physical-verification methodology
- Experience with block or subsystem timing closure
- Experience with the complete physical-design flow
- Expertise with ICV or Calibre for DRC and LVS resolution
- Expertise with IR and EM analysis
- Background in STA, constraint drafting, and timing convergence
- Understanding of full-chip floorplanning and integration
- Scripting ability in Tcl and Python
- Experience with Design Compiler, Fusion Compiler, ICC2, or similar tools
- BS or MS in Electrical Engineering
Responsibilities
- Synthesize, place, and route high-speed designs
- Integrate physical-design blocks into full-chip architecture
- Perform block-level and full-chip physical verification
- Drive timing closure across blocks, partitions, and full chip
- Optimize power, performance, and area
- Resolve DRC and LVS issues
- Perform IR and EM analysis and resolution
- Draft constraints and drive timing convergence
- Support full-chip floorplanning and integration
- Enhance design flows using Tcl and Python
- Work with RTL teams to optimize physical design