Physical Design Engineer Full Chip Implementation

Etched is an AI-hardware company building rack-scale frontier inference clusters.

San Jose, United States
About Etched

Etched co-designs chips, racks, software, and manufacturing systems for efficient inference of frontier AI models, targeting throughput, latency, cost, and power efficiency across prefill and decode workloads.

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Skills

Candidate Availability

Required and preferred rules are kept separate and reflect the wording in the original posting.

About the Role

You will own full-chip implementation from synthesis through GDSII completion. You will manage clocking, multi-mode multi-corner timing closure, constraints, ECOs, physical verification, and tapeout signoff. You will debug layout issues, build repeatable physical-verification methods, optimize PPA, and provide feedback to RTL designers.

Requirements

  • 10+ years of chip-planning, top-level physical-design, and floorplanning experience
  • Experience with full-chip closure on 5 nm or smaller process nodes
  • Experience with Cadence Innovus and Genus or Synopsys Fusion Compiler
  • Experience with Synopsys PrimeTime and Cadence Tempus timing signoff
  • Experience with Pegasus or Calibre physical-verification signoff
  • Experience with hierarchical timing budgets, constraint management, and ECO closure
  • Experience using Cadence Innovus for top-level assembly, routing, and layout fixes

Responsibilities

  • Own full-chip clocking across PVT corners and modes
  • Manage top-level multi-mode multi-corner timing closure
  • Own timing constraints and hierarchical timing budgets
  • Drive functional and timing ECO closure through final tapeout signoff
  • Own physical-verification closure across block, subsystem, and full-chip levels
  • Debug physical-verification violations and fix layout issues using Innovus
  • Build repeatable tapeout-ready physical-verification methodology

Benefits

  • Medical, dental, and vision coverage with generous premium coverage
  • USD 500 monthly credit for waiving medical benefits
  • USD 2,500 monthly housing subsidy for employees living within walking distance of the office
  • Relocation support to San Jose
  • Wellness benefits for fitness and mental health
  • Daily office lunch and dinner
  • Unlimited compute budget subject to ROI justification
Physical Design Engineer Full Chip Implementation at Etched | JobStash