Senior Staff Physical Design Timing Engineer

Skills

About the Role

You will drive timing constraints development, static timing analysis, timing closure, and tapeout signoff for silicon photonics chips. You will collaborate on timing modes and constraints, analyze implementation trade-offs, automate timing ECOs, and document best practices for future projects.

Requirements

• Bachelor’s degree in Electrical Engineering or Computer Engineering
• 12 years of Physical Design experience
• At least 5 years of hands-on ASIC STA, timing constraints development, and timing closure experience with Cadence or Synopsys tools
• Experience managing on-chip variation derates, multi-mode multi-corner constraints, and clock-tree strategies
• Experience with TCL, Python, Perl, or Shell scripting

Responsibilities

• Drive STA signoff for silicon photonics chips at multiple technology nodes
• Analyze fabrication guidelines and incorporate signoff corners, margins, and derates into timing flows
• Collaborate with architecture, RTL, and DFT teams to develop timing modes and constraints
• Analyze power, performance, and area trade-offs for chip implementation flows
• Run full-chip STA and project timing summaries across scenarios
• Use Tempus or PrimeTime to automate timing ECO generation and support physical design implementation
• Document best practices and lessons learned for future projects

Benefits

• Comprehensive health care plan including medical, dental, and vision coverage
• Retirement savings matching program
• Life insurance including basic, voluntary, and AD&D coverage
• Vacation, sick time, and public holidays
• Paid family leave
• Short-term and long-term disability coverage
• Training and development
• Commuter benefits
• Flexible hybrid workplace model
• Equity grants for eligible full-time employees