Senior RTL Engineer
Velaura AI develops ultra-low-power silicon and software technologies for AI compute infrastructure. Its solutions serve hyperscale data centers and Physical AI applications such as robotics, autonomous systems, drones, and edge devices.
Maintainer signals as of 8/23/2026
Funding history
About Velaura AI, Inc.
Velaura AI is an AI compute infrastructure company developing ultra-low-power silicon and software technologies. Its Titan Core™ platform uses proprietary digital chip IP, low-voltage libraries, EDA flows, and design methodologies to improve performance per watt in AI accelerators while maintaining performance, yield, and reliability. The company also applies this technology to Physical AI systems, including industrial robots, autonomous machines, drones, humanoids, and edge devices. Velaura engages hyperscalers, XPU companies, and developers of next-generation AI infrastructure and Physical AI solutions.
Skills
Candidate Availability
Required and preferred rules are kept separate and reflect the wording in the original posting.
About the Role
Own and optimize RTL for key portions of a Physical AI SoC, drive microarchitectural decisions, define hardware interfaces and memory hierarchies, contribute to data movement and control infrastructure, analyze bottlenecks, lead reviews, and mentor junior engineers.
Requirements
- 8+ years designing RTL for complex digital systems or equivalent depth, with ownership of significant blocks or subsystems through tapeout.
- Strong understanding of computer architecture, microarchitecture, and digital design fundamentals.
- Expert-level Verilog and SystemVerilog skills, including lint, CDC, synthesis-aware coding, and low-power intent.
- Strong understanding of performance, power, and area tradeoffs.
- Understanding of memory systems, interconnects, caches, DMA engines, or accelerator architectures.
- Experience with hardware/software co-design and system-level performance optimization.
- Strong debugging and problem-solving skills.
- Ability to work effectively in and technically lead a collaborative, multidisciplinary engineering environment.
Responsibilities
- Own the design, implementation, and optimization of RTL for key SoC components.
- Drive microarchitectural decisions within areas of ownership.
- Define hardware interfaces, execution flows, and memory hierarchies.
- Contribute to compute engines, memory subsystems, interconnect fabrics, control processors, DMA engines, and power-management logic.
- Optimize designs for performance, power, area, scalability, and reliability.
- Analyze performance bottlenecks and propose architectural and implementation improvements.
- Lead design reviews.
- Mentor junior engineers.
Benefits
- Performance-based incentives
- Equity participation
- Medical coverage
- Dental coverage
- Vision coverage
- Paid time off
- Flexible work arrangements
- Professional development opportunities