Design Verification Engineer Internal IP
EtchedVisit Etched website
Etched is an AI-hardware company building rack-scale frontier inference clusters.
San Jose, United States
Funding history
About Etched
Etched co-designs chips, racks, software, and manufacturing systems for efficient inference of frontier AI models, targeting throughput, latency, cost, and power efficiency across prefill and decode workloads.
Skills
Candidate Availability
Required and preferred rules are kept separate and reflect the wording in the original posting.
About the Role
You will develop UVM/SystemVerilog testbenches for compute, DMA, NoC, and memory IP. You will execute verification plans, debug RTL and testbench issues, work with architecture and design partners, support end-to-end bring-up, and improve reusable verification infrastructure and coverage models.
Requirements
- UVM
- SystemVerilog
- Digital design
- Computer architecture
- Datapath verification
- Memory-system verification
- Interconnect verification
- High-throughput fabric verification
Responsibilities
- Develop and maintain UVM/SystemVerilog testbenches for high-performance IP
- Define and execute verification plans
- Debug datapath and protocol issues in RTL and testbench environments
- Validate functionality and design intent with architects and designers
- Partner on end-to-end bring-up and debug coverage
- Improve reusable DV infrastructure, coverage models, and methodology
Benefits
- Medical, dental, and vision coverage
- $500 per month credit for waiving medical benefits
- $2,500 per month housing subsidy for employees living within walking distance of the office
- Relocation support for moves to San Jose
- Wellness benefits
- Daily lunch and dinner
- Unlimited compute budget subject to ROI justification