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Senior Director CAD & Design Methodology

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Velaura AI

Velaura AI develops ultra-low-power compute technology for cloud, edge, and physical AI applications. It also offers Teraflux Bitcoin mining hardware, fleet-management software, and related support for mining operators.

Santa Clara, USA
About Velaura AI

Velaura AI is a semiconductor and technology company that provides patented ultra-low-power silicon design technology, IP, toolflows, and custom chiplet solutions for AI compute platforms. Its customers include hyperscaler and XPU companies seeking reduced power consumption and higher compute efficiency. The company also builds Teraflux Bitcoin mining products, including air-, hydro-, and immersion-cooled miners, ASICs, modular containers, miner firmware, fleet-management software, and enterprise customer support.

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Skills

Candidate Availability

Required and preferred rules are kept separate and reflect the wording in the original posting.

About the Role

You lead the end-to-end ASIC design methodology, engineering infrastructure, and CAD organization. You define tools, automation, and workflows from RTL through signoff, packaging integration, and tapeout; manage EDA tools and licensing; build infrastructure and CI systems; and mentor and scale the CAD and methodology organization.

Requirements

  • Deep understanding of the complete ASIC development lifecycle from architecture and RTL through tapeout
  • Experience developing and owning design methodologies across multiple successful SoC programs
  • Hands-on experience with EDA ecosystems from multiple vendors such as Synopsys Cadence Siemens EDA and Ansys
  • Strong understanding of engineering compute infrastructure distributed scheduling storage systems cloud environments and license management
  • Excellent scripting and automation skills using Python Tcl Bash or similar
  • Strong knowledge of version control continuous integration regression management and reproducible engineering practices
  • Ability to make technical and business decisions involving tools infrastructure budgets licensing and engineering investment
  • Exceptional organizational and leadership skills
  • Excellent communication skills and ability to influence senior technical leaders across disciplines
  • Experience with advanced technology nodes N3 N2 or beyond
  • Experience building CAD organizations in an early-stage semiconductor company
  • Familiarity with AI-assisted engineering workflows and next-generation design automation
  • Experience supporting chiplet-based designs or advanced packaging

Responsibilities

  • Architect and own the end-to-end ASIC development methodology
  • Establish scalable and reproducible design flows across RTL verification synthesis DFT physical design STA physical verification release management and silicon bring-up support
  • Lead the evaluation selection deployment and integration of EDA tools
  • Define the engineering infrastructure strategy for compute storage networking cloud resources scheduling security backup and disaster recovery
  • Build automation frameworks CI/CD pipelines regression systems dashboards and engineering workflows
  • Own EDA licensing strategy vendor relationships procurement budgets IP administration and license compliance
  • Partner with architecture RTL verification physical design packaging software and IT teams
  • Build mentor and scale the CAD and methodology organization

Benefits

  • Equity participation
  • Medical coverage
  • Dental coverage
  • Vision coverage
  • Paid time off
  • Flexible work arrangements