Senior ASIC RTL Design Engineer AI Hardware

11 hours agoSeniorSalary: 200K - 290KSunnyvale, USA Remote Full Time Engineering Jobs by Cerebras Systems, Inc.

Cerebras Systems, Inc.

Cerebras builds wafer-scale AI computing systems and a cloud inference platform for training, fine-tuning, and serving AI models.

Series F+Recently fundedCompany intelligence

Sunnyvale, California, United States

Funding history

Initial Public Offering ($6.4B)Revolving credit facilitySeries H ($1B)

Investors

Moore Strategic Ventures Valor Equity Partners Coatue Alpha Wave Global AMD

About Cerebras Systems, Inc.

Cerebras Systems is an AI-infrastructure company founded in 2015. It sells rack-scale wafer-scale computing systems and provides cloud-based, API-accessible AI inference alongside on-premises deployments.

View jobs by Cerebras Systems, Inc.

Skills

Asic Dft Ethernet Fpga Integration Pcie Python Rdma Rtl Serdes Synthesis Tcl Tcp/Ip Verification

Candidate Availability

Remote · Sunnyvale · Required

Required and preferred rules are kept separate and reflect the wording in the original posting.

About the Role

You will design and develop next-generation wafer-scale-engine RTL and integration solutions. You will drive chip design from functional specification and microarchitecture through RTL development and synthesis, work with physical design, verification, DFT, software, and system partners, and debug silicon functional, timing, and power issues during bring-up.

Requirements

Master’s degree in Computer Science, Electrical Engineering, or equivalent
Ability to work in a hybrid work environment
8+ years of experience delivering complex, high-performance RTL designs
Experience with front-end chip integration and third-party IP integration
Experience in high-performance computing, GPU or CPU designs, machine learning, or related fields
Track record of multiple successful silicon deliveries
Experience collaborating with external vendors
Networking stack experience including TCP/IP, RDMA, and Ethernet
Knowledge of PCIe, CPU interfaces, and Serdes technology
Working knowledge of Python and TCL scripting tools

Responsibilities

Drive chip design from functional specification and microarchitecture through RTL development and synthesis
Collaborate with physical design teams to achieve PPA goals
Collaborate with design verification and DFT teams to improve functional and test coverage
Partner with software and system teams to optimize product performance and features
Debug silicon-level functional, timing, and power issues during bring-up

Benefits