Job for Web3 Beginners
RTL Intern
EtchedVisit Etched website
Etched is an AI-hardware company building rack-scale frontier inference clusters.
San Jose, United States
Funding history
About Etched
Etched co-designs chips, racks, software, and manufacturing systems for efficient inference of frontier AI models, targeting throughput, latency, cost, and power efficiency across prefill and decode workloads.
Skills
Candidate Availability
Required and preferred rules are kept separate and reflect the wording in the original posting.
About the Role
You will help design microarchitecture and implement Verilog logic for machine-learning architectures. You will contribute to RTL block development and participate in design discussions, synthesis, and timing feedback throughout the design cycle.
Requirements
- Progress toward a Bachelor's, Master's, or PhD degree in Electrical Engineering, Computer Engineering, or a related field
- High-speed digital logic familiarity
- ASIC or SoC design-concept exposure
- SystemVerilog, UVM, or Python familiarity
- Verification and test-bench familiarity
- Physical-design-flow and tooling familiarity
- Knowledge of transformers and modern artificial intelligence
Responsibilities
- Design microarchitecture
- Implement logic in Verilog
- Contribute to RTL block development
- Participate in microarchitecture discussions, synthesis, and timing feedback
Benefits
- 12-week paid internship
- Housing support for relocating interns
- Daily office lunch and dinner
- Direct mentorship