Senior Staff Design Verification Engineer
d-MatrixVisit d-Matrix website
AI-infrastructure company producing memory-centric hardware, networking, and software for low-latency generative-AI inference in data centers.
Santa Clara, United States
Funding history
About d-Matrix
d-Matrix develops digital in-memory-compute technology and a full-stack inference platform comprising Corsair accelerators, JetStream networking accelerators, and Aviator software.
Skills
Candidate Availability
Required and preferred rules are kept separate and reflect the wording in the original posting.
About the Role
You will develop and execute verification plans from architecture definition through tape-out and silicon bring-up. You will build UVM or OVM verification environments, write and debug SystemVerilog testbenches, drive coverage closure and failure analysis, and align verification strategy with design schedules.
Requirements
- Bachelor's degree in Electrical Engineering, Computer Science, or a related field with 12+ years of industry experience, or a preferred master's degree with 7+ years
- Experience across the full SoC or IP verification cycle
- ASIC or SoC verification test development and debug experience
- SystemVerilog fluency
- Knowledge of UVM, OVM, or VMM
- Problem-solving skills
Responsibilities
- Develop and execute SoC and IP verification plans
- Build and maintain UVM and OVM verification environments
- Write and debug SystemVerilog testbenches
- Drive root-cause analysis of verification failures
- Define and track coverage closure goals
- Align verification strategy with tape-out schedules
- Improve verification methodology and infrastructure
Benefits
- Medical insurance
- Dental insurance
- Vision insurance
- 401k
- Equity
- Bonus