RTL Designer – Physical AI Compute
Velaura AI develops ultra-low-power compute technology for cloud, edge, and physical AI applications. It also offers Teraflux Bitcoin mining hardware, fleet-management software, and related support for mining operators.
Projects
About Velaura AI
Velaura AI is a semiconductor and technology company that provides patented ultra-low-power silicon design technology, IP, toolflows, and custom chiplet solutions for AI compute platforms. Its customers include hyperscaler and XPU companies seeking reduced power consumption and higher compute efficiency. The company also builds Teraflux Bitcoin mining products, including air-, hydro-, and immersion-cooled miners, ASICs, modular containers, miner firmware, fleet-management software, and enterprise customer support.
Skills
About the Role
You will design and implement RTL for key portions of the SoC, collaborate with architects to develop robust microarchitectures, participate in hardware and software co design discussions spanning AI workloads memory systems runtime software and system architecture, define hardware interfaces execution flows memory hierarchies and performance critical interactions, contribute to compute engines memory subsystems interconnect fabrics control processors DMA engines power management logic and other core SoC infrastructure, optimize designs for performance power area scalability and reliability, partner closely with verification and physical design teams throughout the development cycle, analyze performance bottlenecks and propose architectural and implementation improvements, leverage modern engineering tools, including AI assisted development workflows, to improve productivity, quality, and design exploration, and participate in design reviews and contribute to a culture of technical excellence.
Requirements
- Experience designing RTL for complex digital systems.
- Strong understanding of computer architecture, microarchitecture, and digital design fundamentals.
- Experience with Verilog/SystemVerilog and modern RTL design methodologies.
- Familiarity with performance, power, and area tradeoffs.
- Understanding of memory systems, interconnects, caches, DMA engines, or accelerator architectures.
- Experience with hardware/software co-design and system-level performance optimization.
- Strong debugging and problem-solving skills.
- Ability to work effectively in a collaborative, multidisciplinary engineering environment.
Responsibilities
- Design, implement, and optimize RTL for key portions of the SoC.
- Collaborate with architects to develop robust and efficient microarchitectures.
- Participate in hardware/software co-design discussions spanning AI workloads, memory systems, runtime software, and system architecture.
- Work with software teams to define hardware interfaces, execution flows, memory hierarchies, and performance-critical interactions.
- Contribute to compute engines, memory subsystems, interconnect fabrics, control processors, DMA engines, power-management logic, and other core SoC infrastructure.
- Optimize designs for performance, power, area, scalability, and reliability.
- Partner closely with verification and physical design teams throughout the development cycle.
- Analyze performance bottlenecks and propose architectural and implementation improvements.
- Leverage modern engineering tools, including AI-assisted development workflows, to improve productivity, quality, and design exploration.
- Participate in design reviews and contribute to a culture of technical excellence.
