Power Integrity Engineer

Skills

About the Role

You will own power-integrity methodology from architecture through release. You will perform PDN, AC, DC, thermal, and VRM analyses; define PCB requirements; support design reviews and bring-up; debug rail-level issues; and maintain simulation-to-hardware correlation data.

Requirements

• B.S. or M.S. in Electrical Engineering or a closely related discipline
• 5+ years of hands-on power-integrity experience on high-current, high-performance designs
• Proficiency with power-integrity EDA tools
• Understanding of target impedance methodology, decoupling-network design, plane resonances, and anti-resonance mitigation
• Experience with DC IR-drop analysis, current-density limits, and via and plane current capacity
• Knowledge of VRM fundamentals, buck converters, multiphase design, transient response, and load-line concepts
• Knowledge of multi-layer PCB stack-up design and power-plane allocation strategies

Responsibilities

• Perform pre- and post-layout PDN analysis for high-current ASIC power rails
• Execute DC IR-drop and current-density simulations
• Conduct AC impedance analysis from VRM output through package and die
• Develop and validate VRM models and analyze transient response
• Perform power-plane thermal co-simulation
• Drive power-integrity design-rule checks
• Collaborate on power-delivery architecture and design guidelines
• Support bring-up and debug rail-level issues
• Maintain simulation-to-hardware correlation databases

Benefits

• Medical, dental, and vision packages with generous premium coverage
• $500 per month credit for waiving medical benefits
• Housing subsidy of $2,500 per month for employees living within walking distance of the office
• Relocation support for employees moving to San Jose
• Wellness benefits covering fitness and mental health
• Daily lunch and dinner in the office
• Unlimited compute budget subject to ROI justification