Physical Verification Engineer

Skills

About the Role

You will own block-level and full-chip physical verification and signoff for advanced AI and high-performance computing silicon. You will drive verification from block implementation through full-chip integration and tape-out, debug DRC, LVS, ERC, PERC, antenna, ESD/EOS, and reliability issues, implement physical fixes and ECO changes, develop Tcl and Python, Perl, or Unix shell automation, optimize verification flows, and collaborate across design, CAD, foundry, and EDA functions to achieve signoff closure.

Requirements

• Bachelor’s or Master’s degree in Electrical Engineering, Electronics Engineering, VLSI, Microelectronics, or a related field
• 8+ years of relevant physical verification experience for complex ASIC or SoC designs
• Experience owning block-level or full-chip physical verification signoff
• Hands-on DRC and LVS signoff experience, with PERC and reliability verification exposure
• Experience with advanced FinFET or GAA technologies and production tape-outs at advanced process nodes
• Expertise with Siemens Calibre or Synopsys ICV
• Experience with Cadence Innovus or Synopsys Fusion Compiler for physical implementation and ECO changes
• Experience correlating physical verification results with implementation databases
• Strong Tcl scripting skills and proficiency in Python, Perl, or Unix shell
• Understanding of the impact of physical changes on timing, congestion, routability, signal integrity, power integrity, reliability, and design closure
• Strong debugging, problem-solving, and root-cause-analysis skills
• Excellent communication and cross-functional collaboration skills

Responsibilities

• Own block-level and full-chip physical verification signoff for ASIC and SoC designs
• Drive tape-out readiness and signoff closure through violation triage, root-cause analysis, waiver management, schedule tracking, and convergence
• Execute and debug physical verification using Siemens Calibre and Synopsys IC Validator
• Correlate verification results with Cadence Innovus and Synopsys Fusion Compiler implementation databases
• Perform physical implementation and ECO changes including routing, via, metal-shape, cell, filler, decap, endcap, and power-grid edits
• Define and enhance PERC and reliability verification flows for ESD, EOS, latch-up, resistance, current-density, and high-current checks
• Develop Tcl, Python, Perl, and Unix shell automation for violation analysis, database queries, ECOs, verification execution, and reporting
• Drive physical verification closure for advanced FinFET and GAA technologies
• Influence floorplanning, power-grid planning, and implementation methodology to minimize signoff violations
• Support hierarchical and full-chip physical verification for digital-on-top, mixed-signal, and multi-voltage SoCs
• Ensure physical verification changes preserve timing, congestion, routability, signal integrity, power integrity, reliability, and functionality
• Develop and optimize verification flows for runtime, scalability, robustness, and usability
• Work with CAD teams, foundries, and EDA vendors to qualify technology nodes and rule decks
• Drive density, metal-fill, DFM, DFY, and pattern-matching verification
• Mentor engineers on verification methodology, advanced-node debugging, root-cause analysis, implementation fixes, and tape-out signoff

Benefits

• Performance-based incentives
• Equity participation
• Medical coverage
• Dental coverage
• Vision coverage
• Paid time off
• Flexible work arrangements
• Professional development opportunities