Hardware Validation and Debug Engineer DDR
Graphcore is a SoftBank-owned AI-compute company developing AI processors, systems, and software for machine-learning workloads.
Funding history
About Graphcore
Graphcore develops Intelligence Processing Units (IPUs) and the Poplar SDK for building and running machine-learning applications. It continues operating under the Graphcore name as a wholly owned SoftBank Group subsidiary.
Skills
Candidate Availability
Required and preferred rules are kept separate and reflect the wording in the original posting.
About the Role
You will create and execute validation and debug plans for silicon devices and hardware platforms. You will perform system bring-up, manually test systems in the lab, debug hardware and firmware, analyse DDR margins and signal integrity, resolve issues, and document test procedures and findings.
Requirements
- Hardware debugging
- LPDDR validation and tuning
- Signal integrity analysis
- DDR training and margin analysis
- Protocol-level debugging
- Root-cause analysis
- Low-level system integration
- Ability to work independently
- Board bring-up and subsystem debugging
- Experience with high-bandwidth oscilloscopes, BERT systems, and VNA/TDR equipment
- Hands-on experience with LPDDR5 memory subsystems
- Experience with LPDDR5 compliance testing
Responsibilities
- Perform validation and debug for new hardware platforms
- Debug PCB, power, signal integrity, and interface issues
- Validate and debug high-speed memory and slow-speed interfaces
- Support LPDDR5-9600 initialization, training, timing optimization, margin analysis, and stability validation
- Analyse DDR timing margins, signal integrity, eye diagrams, and training behaviour
- Identify root causes and drive corrective actions across hardware and firmware
- Create bring-up documentation, test procedures, and debug reports