Custom Circuit Design (Sr. Staff / Principal)
Velaura AI develops ultra-low-power compute technology for cloud, edge, and physical AI applications. It also offers Teraflux Bitcoin mining hardware, fleet-management software, and related support for mining operators.
Maintainer signals as of 8/14/2026
Funding history
About Velaura AI
Velaura AI is a semiconductor and technology company that provides patented ultra-low-power silicon design technology, IP, toolflows, and custom chiplet solutions for AI compute platforms. Its customers include hyperscaler and XPU companies seeking reduced power consumption and higher compute efficiency. The company also builds Teraflux Bitcoin mining products, including air-, hydro-, and immersion-cooled miners, ASICs, modular containers, miner firmware, fleet-management software, and enterprise customer support.
Skills
Candidate Availability
Required and preferred rules are kept separate and reflect the wording in the original posting.
About the Role
You will lead the architecture, design, and optimization of high-performance, low-power standard cell libraries and custom digital circuits. You will drive transistor-level innovation, develop arithmetic building blocks, perform circuit verification and reliability sign-off, improve design methodologies, and mentor engineers.
Requirements
- 10+ years of experience in custom digital circuit design, standard cell development, or memory circuit design
- Expertise in transistor-level CMOS circuit design for advanced technology nodes
- Experience designing and optimizing high-performance, low-power standard cell libraries
- Understanding of FinFET and GAA technologies
- Experience with HSPICE, PrimeSim XA, or Spectre
- Experience with parasitic extraction using StarRC or Quantus
- Knowledge of statistical verification, Monte Carlo analysis, and variation-aware circuit design
- Experience with reliability verification including EM, IR-drop, aging, and self-heating
- Master's or Ph.D. in Electrical Engineering, Electronics Engineering, or a related discipline preferred
- Experience developing automation using Python, Tcl, or Perl preferred
Responsibilities
- Lead standard cell architecture, design, and optimization
- Design and optimize transistor-level circuits
- Architect and develop arithmetic building blocks
- Develop schematics using Cadence Virtuoso
- Perform circuit verification across PVT corners
- Drive statistical verification using Monte Carlo methodologies
- Own reliability sign-off activities
- Drive low-power circuit innovations
- Optimize layouts for LDE, manufacturability, coloring compliance, matching, and pin accessibility
- Drive design methodology improvements and automation initiatives
- Mentor engineers and provide technical leadership
Benefits
- Performance-based incentives
- Equity participation
- Medical coverage
- Dental coverage
- Vision coverage
- Paid time off
- Flexible work arrangements
- Professional development opportunities
