ASIC Physical Design Engineer

Skills

About the Role

You will implement physical-design blocks from floorplanning through tapeout. You will run implementation and signoff flows, pursue timing closure, analyze power and physical-verification issues, automate work with scripts, and collaborate with RTL, synthesis, DFT, packaging, and backend partners.

Requirements

• BS/MS in EE/CE or a related field
• 0–3 years of physical design experience
• Physical design
• Floorplanning
• Placement
• Clock tree synthesis
• Routing
• Timing closure
• Static timing analysis
• Innovus or ICC2
• DRC
• LVS
• Tcl or Python
• Tapeout
• IR drop
• Electromigration
• Signal integrity
• VLSI design
• Computer architecture
• AI accelerator
• SRAM
• SerDes
• LPDDR
• Chiplet
• Advanced packaging

Responsibilities

• Implement blocks through floorplanning, macro placement, and power planning.
• Run clock tree synthesis, place and route, routing optimization, and timing closure.
• Support signal-integrity, IR/EM, ECO, metal-fill, and tapeout signoff activities.
• Maintain and improve power-grid, power/ground-tile, and bump-planning flows.
• Run congestion analysis and wire estimation.
• Apply hierarchical implementation and partitioning strategies.
• Run and debug Innovus-based implementation flows.
• Write Tcl and Python scripts to automate tasks and parse reports.
• Analyze and fix timing, power, area, congestion, DRC, LVS, EM, and IR issues.
• Work with backend design-services partners and participate in implementation reviews.
• Use AI-enabled tools for QoR, congestion, routing, and floorplan analysis.

Benefits

• Company-paid medical, dental, and vision insurance for employees and dependents
• Company-paid life and disability coverage
• Supplemental hospital, critical illness, and accident coverage
• Unlimited paid time off
• 13 paid company holidays
• Remote-first work
• Company-provided computer and home office setup
• Equity
• 401(k) matching from day one
• H-1B visa transfer support for eligible candidates