ASIC Design Engineer

Skills

About the Role

You will implement and verify SystemVerilog RTL for assigned ASIC and SoC blocks. You will support front-end checks, timing and PPA optimization, interface integration, automation, verification collaboration, and silicon bring-up while building ownership of the full front-end design flow.

Requirements

• BS/MS in EE/CE or a related field
• 0–3 years of ASIC/SoC RTL design experience
• SystemVerilog or Verilog
• Digital design
• Clock domain crossing
• Simulation
• Lint
• Synthesis
• Static timing analysis
• AMBA AXI, AHB, or APB
• DDR or HBM
• PCIe
• Cache and memory hierarchy
• Datapath design
• Python or Tcl
• Computer architecture
• AI/ML accelerator design
• SystemVerilog Assertions
• Formal verification
• Low-power design
• UPF
• cocotb or UVM
• RISC-V
• FPGA prototyping
• Chip tapeout

Responsibilities

• Implement parameterized SystemVerilog RTL for assigned blocks.
• Contribute to microarchitecture documentation and define block-level interfaces.
• Add assertions and follow clocking, reset, and power-intent guidelines.
• Run and debug lint, CDC/RDC, and synthesis checks.
• Support timing analysis and block-level timing fixes.
• Track PPA metrics and propose optimizations.
• Support integration of AXI, DMA, and memory-controller IP.
• Write and maintain Python, Tcl, and Make scripts.
• Review test plans, debug failures, and close coverage with Verification.
• Correlate RTL behavior with architecture and performance models.
• Participate in bring-up and post-silicon debug.
• Present work in design reviews and incorporate feedback.

Benefits

• Equity
• Flexible work environment